PIC18F87K90 Datasheet, PDF (346/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
TABLE 21-4: REGISTERS ASSOCIATED WITH I²C™ OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF RBIF
73
PIR1
—
ADIF
RC1IF
TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF 75
PIE1
—
ADIE
RC1IE
TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE 75
IPR1
—
ADIP
RC1IP
TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP 75
PIR2
OSCFIF
—
SSP2IF BLC2IF BCL1IF HLVDIF TMR3IF TMR3GIF 75
PIE2
OSCFIE
—
SSP2IE BLC2IE BCL1IE HLVDIE TMR3IE TMR3GIE 75
IPR2
OSCFIP
—
SSP2IP BLC2IP BCL1IP HLVDIP TMR3IP TMR3GIP 75
PIR3
TMR5GIF LCDIF
RC2IF
TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 75
PIE3
TMR5GIE LCDIE
RC2IE
TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 75
IPR3
TMR5GIP LCDIP
RC2IP
TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 75
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 76
TRISD
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 76
SSP1BUF MSSP1 Receive Buffer/Transmit Register
74
SSP1ADD
MSSP1 Address Register (I²C™ Slave mode),
MSSP1 Baud Rate Reload Register (I²C Master mode)
74
SSP1MSK⁽¹⁾ MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1 MSK0
—
SSP1CON1 WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 74
SSP1CON2
GCEN
GCEN
ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
ACKSTAT ADMSK5⁽²⁾ ADMSK4⁽²⁾ ADMSK3⁽²⁾ ADMSK2⁽²⁾ ADMSK1⁽²⁾
SEN
SEN
74
SSP1STAT SMP
CKE
D/A
P
S
R/W
UA
BF
74
SSP2BUF MSSP2 Receive Buffer/Transmit Register
80
SSP2ADD
MSSP2 Address Register (I²C Slave mode),
MSSP2 Baud Rate Reload Register (I²C Master mode)
80
SSP2MSK⁽¹⁾ MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1 MSK0
—
SSP2CON1 WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 80
SSP2CON2
GCEN
GCEN
ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
ACKSTAT ADMSK5⁽²⁾ ADMSK4⁽²⁾ ADMSK3⁽²⁾ ADMSK2⁽²⁾ ADMSK1⁽²⁾
SEN
SEN
81
SSP2STAT SMP
CKE
D/A
P
S
R/W
UA
BF
80
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I²C™ mode.
Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I²C™
Slave operating modes in 7-Bit Masking mode. See Section 21.4.3.4 “7-Bit Address Masking Mode” for
more details.
2: Alternate bit definitions for use in I²C Slave mode operations only.
DS39957B-page 346
Preliminary
 2010 Microchip Technology Inc.