PIC18F87K90 Datasheet, PDF (361/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
FIGURE 22-7:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1
Start
bit 7/8 Stop
bit
bit
bit 0
Word 1
RCREGx
Start
bit 7/8 Stop bit
bit
Word 2
RCREGx
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 22-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
73
PIR1
—
ADIF
RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF
75
PIE1
—
ADIE
RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE
75
IPR1
—
ADIP
RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP
75
PIR3
TMR5GIF LCDIF
RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF
75
PIE3
TMR5GIE LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 75
IPR3
TMR5GIP LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 75
RCSTA1
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
75
RCREG1 EUSART1 Receive Register
75
TXSTA1
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
75
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
77
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte
74
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte
75
RCSTA2
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
79
RCREG2 EUSART2 Receive Register
80
TXSTA2
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
79
BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
79
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte
80
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte
80
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 361