PIC18F87K90 Datasheet, PDF (69/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
5.2 Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
5.3 Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 5-2.
When the device starts normal operation (exiting the
Reset condition), device operating parameters (such
as voltage, frequency and temperature) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
Power-on Reset events are captured by the POR bit
(RCON<1>). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs and does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.
5.4 Brown-out Reset (BOR)
The PIC18F87K90 family has four BOR modes:
• High-Power BOR
• Medium Power BOR
• Low-Power BOR
• Zero-Power BOR
Each power mode is selected by the BORPWR<1:0>
setting (CONFIG2L<6:5>). For low, medium and high-
power BOR, the module monitors the VDD depending
on the BORV<1:0> setting (CONFIG1L<3:2>). A BOR
event re-arms the Power-on Reset. It also causes a
Reset depending on which of the trip levels has been
set: 1.8V, 2V, 2.7V or 3V. The typical (IBOR) for the
Low and Medium Power BOR will be 0.75 A and 3 A.
In Zero-Power BOR (ZPBORMV), the module monitors
the VDD voltage and re-arms the POR at about 2V.
ZPBORMV does not cause a Reset, but re-arms the
POR.
The BOR accuracy varies with its power level. The
lower the power setting, the less accurate the BOR trip
levels are. So, the high-power BOR has the highest
accuracy and the low-power has the lowest accuracy.
The trip levels (BVDD, parameter D005), current
consumption (Section 31.2 “DC Characteristics:
Power-Down and Supply Current PIC18F87K90
Family (Industrial)”) and time required below BVDD
(TBOR, parameter 35) can all be found in Section 31.0
“Electrical Characteristics”
FIGURE 5-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD VDD
D
R
C
R1
MCLR
PIC18F87K90
Note 1:
2:
3:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode, D, helps discharge the capacitor
quickly when VDD powers down.
R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
R1  1 k will limit any current flowing into
MCLR from external capacitor, C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
5.4.1 DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
LP-BOR cannot be detected with the BOR bit in the
RCON register. LP-BOR can rearm the POR and can
cause a Power-on Reset.
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 69