PIC18F87K90 Datasheet, PDF (44/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
3.3.1 OSC1/OSC2 OSCILLATOR
The OSC1/OSC2 oscillator block is used to provide the
oscillator modes and frequency ranges:
Mode
Design Operating Frequency
LP
XT
HS
EC
EXTRC
31.25-100 kHz
100 kHz to 4 MHz
4 MHz to 25 MHz
0 to 64 MHz (external clock)
0 to 4 MHz (external RC)
The crystal-based oscillators (XT, HS and LP) have a
built-in start-up time. The operation of the EC and
EXTRC clocks is immediate.
3.3.2 CLOCK SOURCE SELECTION
The System Clock Select bits, SCS<1:>0
(OSCCON2<1:0>), select the clock source. The avail-
able clock sources are the primary clock defined by the
OSC<3:0> Configuration bits, the secondary clock
(SOSC oscillator) and the internal oscillator. The clock
source changes after one or more of the bits is written
to, following a brief clock transition interval.
The OSTS (OSCCON<3>) and SOSCRUN
(OSCCON2<6>) bits indicate which clock source is
currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The SOSCRUN bit
indicates when the SOSC oscillator (from Timer1/3/5/7)
is providing the device clock in secondary clock modes.
In power-managed modes, only one of these bits will
be set at any time. If neither of these bits is set, the
INTRC is providing the clock, or the internal oscillator
has just started and is not yet stable.
The IDLEN bit (OSCCON<7>) determines if the device
goes into Sleep mode or one of the Idle modes when
the SLEEP instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
Note 1: The secondary oscillator must be enabled
to select the secondary clock source. The
SOSC oscillator is enabled by setting the
SOSCGO bit in the OSCCON2 register
(OSCCON<3>). If the SOSC oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP instruction will be ignored.
2: It is recommended that the secondary
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the SOSC
oscillator starts.
3.3.2.1
System Clock Selection and Device
Resets
Since the SCS bits are cleared on all forms of Reset,
this means the primary oscillator defined by the
OSC<3:0> Configuration bits is used as the primary
clock source on device Resets. This could either be the
internal oscillator block by itself, or one of the other
primary clock source (HS, EC, XT, LP, External RC and
PLL-enabled modes).
In those cases when the internal oscillator block, with-
out PLL, is the default clock on Reset, the Fast RC
oscillator (INTOSC) will be used as the device clock
source. It will initially start at 8 MHz; the postscaler
selection that corresponds to the Reset value of the
IRCF<2:0> bits (‘110’).
Regardless of which primary oscillator is selected,
INTRC will always be enabled on device power-up. It
serves as the clock source until the device has loaded
its configuration values from memory. It is at this point
that the OSC Configuration bits are read and the
oscillator selection of the operational mode is made.
Note that either the primary clock source or the internal
oscillator will have two bit setting options for the possible
values of the SCS<1:0> bits, at any given time.
3.3.3 OSCILLATOR TRANSITIONS
PIC18F87K90 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
3.4 External Oscillator Modes
3.4.1
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS (HS MODES)
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 3-2 shows the pin
connections.
The oscillator design requires the use of a crystal rated
for parallel resonant operation.
Note:
Use of a crystal rated for series resonant
operation may give a frequency out of the
crystal manufacturer’s specifications.
DS39957B-page 44
Preliminary
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