PIC18F87K90 Datasheet, PDF (560/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
Selecting Peripheral Module Control................................... 58
Serial Clock, SCKx............................................................ 301
Serial Data In (SDIx) ......................................................... 301
Serial Data Out (SDOx)..................................................... 301
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................. 483
Shoot-Through Current ..................................................... 265
Slave Select (SSx) ............................................................ 301
SLEEP............................................................................... 484
Software Simulator (MPLAB SIM)..................................... 501
Special Event Trigger. See Compare (CCP Module).
Special Event Trigger. See Compare (ECCP Mode).
SSPOV.............................................................................. 337
SSPOV Status Flag........................................................... 337
SSPxSTAT Register
R/W Bit .............................................................. 316, 319
SSx.................................................................................... 301
Stack Full/Underflow Resets ............................................... 87
SUBFSR............................................................................ 495
SUBFWB........................................................................... 484
SUBLW ............................................................................. 485
SUBULNK ......................................................................... 495
SUBWF ............................................................................. 485
SUBWFB........................................................................... 486
SWAPF ............................................................................. 486
T
Table Pointer Operations (table) ....................................... 112
Table Reads/Table Writes................................................... 87
TBLRD .............................................................................. 487
TBLWT .............................................................................. 488
Timer0 ............................................................................... 181
Associated Registers ................................................ 183
Operation .................................................................. 182
Overflow Interrupt ..................................................... 183
Prescaler ................................................................... 183
Switching Assignment....................................... 183
Prescaler Assignment (PSA Bit) ............................... 183
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 183
Reads and Writes in 16-Bit Mode ............................. 182
Source Edge Select (T0SE Bit)................................. 182
Source Select (T0CS Bit) .......................................... 182
Timer1 ............................................................................... 185
16-Bit Read/Write Mode............................................ 189
Associated Registers ................................................ 195
Clock Source Selection ............................................. 187
Gate .......................................................................... 191
Interrupt..................................................................... 190
Operation .................................................................. 187
Oscillator ................................................................... 185
Resetting, Using the ECCP
Special Event Trigger........................................ 191
SOSC Oscillator ........................................................ 189
Layout Considerations ...................................... 190
Use as a Clock Source ..................................... 190
TMR1H Register ....................................................... 185
TMR1L Register ........................................................ 185
Timer2 ............................................................................... 197
Associated Registers ................................................ 198
Interrupt..................................................................... 198
Operation .................................................................. 197
Output ....................................................................... 198
PR2 Register............................................................. 246
TMR2 to PR2 Match Flag (TMR2IF Bit) .................... 136
TMR2 to PR2 Match Interrupt ................................... 246
Timer3/5/7......................................................................... 199
16-Bit Read/Write Mode ........................................... 204
Associated Registers ................................................ 209
Gates ........................................................................ 204
Operation .................................................................. 203
Overflow Interrupt ............................................. 199, 208
SOSC Oscillator........................................................ 199
Use as a Clock Source ..................................... 204
Special Event Trigger (ECCP) .................................. 208
TMRxH Register ....................................................... 199
TMRxL Register........................................................ 199
Timer4/6/8/10/12............................................................... 211
Associated Registers ................................................ 213
Interrupt .................................................................... 212
Operation .................................................................. 211
Output ....................................................................... 212
Outputs, PWM Time Base for ECCP ........................ 212
Postscaler. See Postscaler, Timer4/6/8/10/12.
Prescaler. See Prescaler, Timer4/6/8/10/12.
PRx Register............................................................. 211
TMRx Register.......................................................... 211
TMRx to PRx Match Interrupt ........................... 211, 212
Timing Diagrams
A/D Conversion......................................................... 539
Automatic Baud Rate Calculation ............................. 356
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................. 363
Auto-Wake-up Bit (WUE) During Sleep .................... 363
Baud Rate Generator with Clock Arbitration............. 334
BRG Overflow Sequence.......................................... 356
BRG Reset Due to SDAx Arbitration During
Start Condition.................................................. 343
Brown-out Reset (BOR)............................................ 524
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 344
Bus Collision During a Repeated Start
Condition (Case 2)............................................ 344
Bus Collision During a Start Condition
(SCLx = 0) ........................................................ 343
Bus Collision During a Stop Condition (Case 1) ....... 345
Bus Collision During a Stop Condition (Case 2) ....... 345
Bus Collision During Start Condition
(SDAx Only)...................................................... 342
Bus Collision for Transmit and Acknowledge ........... 341
Capture/Compare/PWM ........................................... 528
CLKO and I/O ........................................................... 523
Clock Synchronization .............................................. 327
Clock/Instruction Cycle ............................................... 88
EUSART Asynchronous Reception .......................... 361
EUSART Asynchronous Transmission ..................... 358
EUSART Asynchronous Transmission
(Back-to-Back).................................................. 358
EUSART Synchronous Master Transmission........... 365
EUSART/AUSART Synchronous Receive
(Master/Slave) .................................................. 537
EUSART/AUSART Synchronous Transmission
(Master/Slave) .................................................. 537
Example SPI Master Mode (CKE = 0) ...................... 529
Example SPI Master Mode (CKE = 1) ...................... 530
Example SPI Slave Mode (CKE = 0) ........................ 531
Example SPI Slave Mode (CKE = 1) ........................ 532
External Clock........................................................... 521
Fail-Safe Clock Monitor (FSCM)............................... 444
First Start Bit Timing ................................................. 335
Full-Bridge PWM Output........................................... 260
DS39957B-page 560
Preliminary
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