PIC18F87K90 Datasheet, PDF (347/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
22.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of two
serial I/O modules. (Generically, the EUSART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex,
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break recep-
tion and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN/J2602 bus) systems.
All members of the PIC18F87K90 family are equipped
with two independent EUSART modules, referred to as
EUSART1 and EUSART2. They can be configured in
the following modes:
• Asynchronous (full duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half duplex) with
selectable clock polarity
• Synchronous – Slave (half duplex) with selectable
clock polarity
The pins of EUSART1 and EUSART2 are multiplexed
with the functions of PORTC (RC6/TX1/CK1/
SEG27 and RC7/RX1/DT1/SEG28) and PORTG
(RG1/TX2/CK2/AN19/C3OUT and RG2/RX2/DT2/
AN18/C3INA), respectively. In order to configure
these pins as an EUSART:
• For EUSART1:
- SPEN (RCSTA1<7>) bit must be set (= 1)
- TRISC<7> bit must be set (= 1)
- TRISC<6> bit must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- TRISC<6> bit must be set (= 1) for
Synchronous Slave mode
• For EUSART2:
- SPEN (RCSTA2<7>) bit must be set (= 1)
- TRISG<2> bit must be set (= 1)
- TRISG<1> bit must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- TRISC<6> bit must be set (= 1) for
Synchronous Slave mode
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The operation of each Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTAx)
• Receive Status and Control (RCSTAx)
• Baud Rate Control (BAUDCONx)
These are detailed in Register 22-1, Register 22-2 and
Register 22-3, respectively, on the following pages.
Note:
Throughout this section, references to
register and bit names that may be associ-
ated with a specific EUSART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the
Receive Status register for either
EUSART1 or EUSART2.
 2010 Microchip Technology Inc.
Preliminary
DS39957B-page 347