PIC18F87K90 Datasheet, PDF (164/566 Pages) Microchip Technology – 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC18F87K90 FAMILY
11.5 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISD and LATD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note: These pins are configured as digital inputs
on any device Reset.
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, RDPU (PADCFG1<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
All of the PORTD pins are multiplexed with LCD
segment drives that are controlled by bits in the
LCDSE0 register. RD0 is multiplexed with the CTMU
pulse generator output.
I/O port functionality is only available when the LCD
segments are disabled.
The PORTD also has the I²C and SPI functionality on
RD4, RD5 and RD6. The pins for SPI are also configu-
rable for open-drain output. Open-drain configuration is
selected by setting the SSPxOD control bits in the
ODCON1 register.
RD0 has a CTMU functionality. RD1 has the functionality
for a Timer5 clock input and also Timer7 has functionality
for an external clock gate input.
EXAMPLE 11-4: INITIALIZING PORTD
CLRF
CLRF
MOVLW
MOVWF
PORTD
LATD
0CFh
TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
DS39957B-page 164
Preliminary
 2010 Microchip Technology Inc.