71M6545 Datasheet, PDF (95/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
Name
RTC_SBSC[7:0]
RTC_TMIN[5:0]
RTC_THR[4:0]
RTC_WR
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
RTM_E
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
SECURE
SLEEP
SPI_CMD
SPI_E
SPI_SAFE
v1.0
Data Sheet 71M6545/H
Location
2892[7:0]
289E[5:0]
Rst Wk Dir
–– R
0 – R/W
289F[4:0] 0 – R/W
2890[7] 0 0 R/W
2893[5:0]
2894[5:0]
2895[4:0]
2896[2:0]
2897[4:0]
2898[3:0]
2899[7:0]
––
––
––
– – R/W
––
––
––
2106[1]
210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
0 0 R/W
00
00
0 0 R/W
00
00
SFR B2[6] 0 0 R/W
28B2[7] 0 0 W
SFR FD[7:0] – – R
270C[4] 1 1 R/W
270C[3] 0 0 R/W
Description
Time remaining since the last 1 second boundary. LSB=1/128 second.
The target minutes register. See RTC_THR below.
The target hours register. The RTC_T interrupt occurs when RTC_MIN [5:0] becomes
equal to RTC_TMIN[5:0] and RTC_HR[4:0] becomes equal to RTC_THR[4:0].
Freezes the RTC shadow register so it is suitable for MPU writes. When RTC_WR is
cleared, the contents of the shadow register are written to the RTC counter on the
next RTC clock (~1 kHz). When RTC_WR is read, it returns 1 as long as RTC_WR is
set. It continues to return one until the RTC counter actually updates.
The RTC interface. These are the year, month, day, hour, minute and second
parameters for the RTC. The RTC is set by writing to these registers. Year 00 and all
others divisible by 4 are defined as a leap year.
SEC 00 to 59
MIN 00 to 59
HR 00 to 23 (00=Midnight)
DAY 01 to 07 (01=Sunday)
DATE01 to 31
MO 01 to 12
YR 00 to 99
Each write operation to one of these registers must be preceded by a write to 0x20A0.
Real Time Monitor enable. When 0, the RTM output is low.
Four RTM probes. Before each CE code pass, the values of these registers are
serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0.
Note that RTM0 is 10 bits wide. The others assume the upper two bits are 00.
Inhibits erasure of page 0 and flash memory addresses above the beginning of CE code
as defined by CE_LCTN[5:0]. Also inhibits the reading of flash memory by external
devices (SPI or ICE port).
Puts the 71M6545/H to sleep. Ignored if system power is present. The 71M6545/H
wakes when the Wake timer times out, when push button is pushed, or when system
power returns.
SPI command. 8-bit command from the bus master.
SPI port enable. Enables the SPI interface on pins SPI_DI, SPI_DO, SPI_CSZ and
SPI_CKI.
Limits SPI writes to SPI_CMD and a 16 byte region in DRAM. No other writes are
permitted.
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