71M6545 Datasheet, PDF (78/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
stored by the MPU in five CE RAM locations GAIN_ADJ0-GAIN_ADJ5 (CE RAM 0x40-0x44). The
demonstration code thus provides a suitable implementation of temperature compensation, but other
methods are possible in MPU firmware by utilizing the on-chip temperature sensor while storing the sample
gain adjustment results in the CE RAM GAIN_ADJn storage locations. The demonstration code maintains
five separate sets of PPMC and PPMC2 coefficients and computes five separate GAIN_ADJn values
based on the sensed temperature using the equation below:
10 ⋅TEMP _ X ⋅ PPMC 100 ⋅TEMP _ X ² ⋅ PPMC2
GAIN _ ADJx = 16385 +
+
2¹⁴
2 ²³
The GAIN_ADJn values stored by the MPU in CE RAM are used by the CE to gain adjust (i.e., multiply)
the sample in each corresponding sensor channel. A GAIN_ADJx value of 16,384 (i.e., 2¹⁴)corresponds to
unity gain, while values less than 16,384 attenuate the samples and values greater than 16,384 amplify
the samples.
In the above equation, TEMP_X is the deviation from nominal or calibration temperature expressed in
multiples of 0.1 °C. The 10x and 100x factors seen in the above equation are due to 0.1 ^oC scaling of
TEMP_X. For example, if the calibration (reference) temperature is 22 °C and the measured temperature
is 27 °C, then 10*TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 °C deviation from 22 °C.
In the demonstration code, TEMP_X is calculated in the MPU from the STEMP[10:0] temperature sensor
reading using the equation provided below and is scaled in 0.1°C units. See 2.5.5 71M6545/H
Temperature Sensor on page 53 for the equation to calculate temperature in °C from the STEMP[10:0]
reading.
Table 58 shows the five GAIN_ADJx equation output storage locations and the voltage or current
measurements for which they compensate.
Table 58: GAIN_ADJx Compensation Channels (Figure 3, Figure 28, Table 2)
Gain Adjustment Output
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
GAIN_ADJ3
GAIN_ADJ4
CE RAM Address
0x40
0x41
0x42
0x43
0x44
Sensor Channel(s)
(pin names)
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
IADC0-IADC1
IADC2-IADC3
IADC4-IADC5
IADC6-IADC7
Compensation For:
VREF in 71M6545/H and Voltage
Divider Resistors
VREF in 71M6545/H, CT and Burden
Resistor (Neutral Current)
VREF in 71M6545/H, CT and Burden
Resistor (Phase A)
VREF in 71M6545/H, CT and Burden
Resistor (Phase B)
VREF in 71M6545/H, CT and Burden
Resistor (Phase C)
In the demonstration code, the shape of the temperature compensation second-order parabolic curve is
determined by the values stored in the PPMC (1^st order coefficient) and PPMC2 (2^nd order coefficient),
which are typically setup by the MPU at initialization time from values that are stored in EEPROM.
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the five GAIN_ADJx channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected VREF temperature variation and optionally the
corresponding sensor circuit (i.e., the CT and burden resistor for current channels or the resistor divider
network for the voltage channels).
In the 71M6545 (±0.5% energy accuracy), the required VREF compensation coefficients PPMC and
PPMC2 are calculated from readable on-chip non-volatile fuses (see 4.5.2Temperature Coefficients for
the 71M6545). These coefficients are designed to achieve ±40 ppm/°C for VREF.
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