71M6545 Datasheet, PDF (47/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
Data Sheet 71M6545/H
The page erase sequence is:
• Write the page address to FLSH_PGADR[6:0] (SFR 0xB7[7:1]).
• Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94).
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE
operations, such as reading via the SPI or ICE port, are blocked. This guarantees the security of the user’s
MPU and CE program code. Security is enabled by MPU code that is executed in a 64 CKMPU cycle
pre-boot interval before the primary boot sequence begins. Once security is enabled, the only way to
disable it is to perform a global erase of the flash, followed by a chip reset.
The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the
ICE is inhibited. A read-only status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU.
Upon completion of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.
The security enable bit, SECURE (SFR 0xB2[6]), is reset whenever the chip is reset. Hardware associated
with the bit allows only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security
feature but may not reset it. Once SECURE is set, the pre-boot and CE code are protected from erasure,
and no external read of program code is possible.
Specifically, when the SECURE bit is set, the following applies:
• The ICE is limited to bulk flash erase only.
• Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.
• Write operations to page zero, whether by MPU or ICE are inhibited.
The 71M6545/H also includes hardware to protect against unintentional Flash write and erase. To enable
flash write and erase operations, a 4-bit hardware key that must be written to the FLSH_UNLOCK[3:0] field.
The key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] is not ‘0010’, the Flash erase and write operation
is inhibited by hardware. Proper operation of this security key requires that there be no firmware function that
writes ‘0010’ to FLSH_UNLOCK[3:0]. The key should be written by the external SPI master, in the case of
SPI flash programming (SFM mode), or through the ICE interface in the case of ICE flash programming.
When a boot loader is used, the key should be sent to the boot load code which then writes it to
FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not automatically reset. It should be cleared when the SPI or
ICE has finished changing the Flash. Table 38 summarizes the I/O RAM registers used for flash security.
Name
Location
FLSH_UNLOCK[3:0] 2702[7:4]
SECURE
SFR B2[6]
Table 38: Flash Security
Rst Wk Dir Description
0
0 R/W Must be a 2 to enable any flash modification.
See the description of Flash security for
more details.
0
0 R/W Inhibits erasure of page 0 and flash addresses
above the beginning of CE code as defined
by CE_LCTN[5:0](I/O RAM 0x2109[5:0]).
Also inhibits the read of flash via the ICE
and SPI ports.
SPI Flash Mode
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6545/H contains a Special Flash Mode (SFM) that facilitates initial (production) programming of the
flash memory. When the 71M6545/H is in SFM mode, the SPI interface can erase, read, and write the
flash. Other memory elements such as XRAM and I/O RAM are not accessible to the SPI in this mode.
In order to protect the flash contents, several operations are required before the SFM mode is successfully
invoked.
Details on the SFM can be found in 2.5.12 SPI Slave Port.
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