71M6545 Datasheet, PDF (56/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
Table 45: Data/Direction Registers for DIO19-25 and DIO28-29
DIO
19 20 21 22 23 24 25
28 29
Pin #
14 13 12 11 10 9 8
76
DIO Data Register
Direction Register:
0 = input, 1 = output
19 20 21 22 23 24 25
DIO16[0] to DIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
19 20 21 22 23 24 25
DIO16[1] to DIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
28 29
28 29
Table 46: Data/Direction Registers for DIO55
DIO
Pin #
DIO Data Register
Direction Register:
0 = input, 1 = output
– – – – 55 – – –
– – – – 32 – – –
– – – – 55 – – –
DIO51[0] to DIO55[0]
(I/O RAM 0x2443[0] to 0x2447[0])
– – – – 55 – – –
DIO51[1] to DIO55[1]
(I/O RAM 0x2443[1] to 0x2447[1])
The PB pin is a dedicated digital input and is not part of the DIO system.
The CE features pulse counting registers and the CE pulse outputs are directly routed to the
pulse interrupt input. Thus, no routing of pulse signals to external pins is required in order to
generate pulse interrupts.
A 3-bit configuration word, I/O RAM register DIO_Rn[2:0] (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can
be used for pins DIO2 through DIO11 (when configured as DIO) and PB to individually assign an internal
resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures the PB
pin). This way, DIO pins can be tracked even if they are configured as outputs. Table 47 lists the
internal resources which can be assigned using DIO_R2[2:0] (also called DIO_RPB[2:0]) through
DIO_R11[2:0] and DIO_RPB[2:0]. If more than one input is connected to the same resource, the resources
are combined using a logical OR.
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits
Value in DIO_Rn[2:0]
Resource Selected for DIOn or PB Pin
0
None
1
Reserved
2
T0 (counter0 clock)
3
T1 (counter1 clock)
4
High priority I/O interrupt (INT0)
5
Low priority I/O interrupt (INT1)
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown
in Figure 14, right), not source it from V3P3D (as shown in Figure 14, left). This is due to the
resistance of the internal switch that connects V3P3D to V3P3SYS.
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for example
with pull-up or pull-down resistors, should be avoided. Violating this rule leads to increased
quiescent current from a battery connected to the VBAT_RTC pin during SLP mode.
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