71M6545 Datasheet, PDF (29/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
VB
IB
Data Sheet 71M6545/H
IA
61.04 µs
CK32
(32768 Hz)
MUX
STATE
S
0
VA
IC
VC
61.04 µs
Multiplexer Frame (15 x 30.518 µs = 457.8 µs)
MUX_DIV = 7 Conversions
61.04 µs
1
2
3
4
5
Figure 10: Samples from Multiplexer Cycle (Frame)
ID
61.04 µs
30.5 µs
Settle
6
S
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 11: Accumulation Interval
Figure 11 shows the accumulation interval resulting from SUM_SAMPS[12:0] = 1819 (I/O RAM
0x2107[4:0] and 0x2108[7:0]), consisting of 1819 samples of 457.8 µs each, followed by the XFER_BUSY
interrupt. The sampling in this example is applied to a 50 Hz signal. There is no correlation between the
line signal frequency and the choice of SUM_SAMPS[12:0]. Furthermore, sampling does not have to start
when the line voltage crosses the zero line, and the length of the accumulation interval need not be an
integer multiple of the signal cycles.
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