71M6545 Datasheet, PDF(7/134 Page) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

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71M6545 Datasheet, PDF (7/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

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PDS_6545_009

Data Sheet 71M6545/H

Table 49: EECTRL Bits for the 3-wire Interface ....................................................................................... 58

Table 50: SPI Transaction Fields ........................................................................................................... 61

Table 51: SPI Command Sequences ..................................................................................................... 62

Table 52: SPI Registers......................................................................................................................... 62

Table 53: TMUX[4:0] Selections ............................................................................................................ 64

Table 54: TMUX2[4:0] Selections........................................................................................................... 65

Table 55: Available Circuit Functions ..................................................................................................... 67

Table 56: VSTAT[2:0] (SFR 0xF9[2:0]) ................................................................................................... 68

Table 57: GAIN_ADJn Compensation Channels (Figure 2, Figure 27, Table 1) ...................................... 76

Table 58: GAIN_ADJx Compensation Channels (Figure 3, Figure 28, Table 2) ...................................... 78

Table 59: I/O RAM Map â Functional Order, Basic Configuration ........................................................... 82

Table 60: I/O RAM Map â Functional Order ........................................................................................... 84

Table 61: I/O RAM Map â Alphabetical Order ........................................................................................ 88

Table 62. Info Page Trim Fuses............................................................................................................. 98

Table 63: CE EQU[2:0] Equations and Element Input Mapping ............................................................ 101

Table 64: CE Raw Data Access Locations ........................................................................................... 102

Table 65: CESTATUS Register.............................................................................................................. 103

Table 66: CESTATUS Bit Definitions...................................................................................................... 103

Table 67: CECONFIG Register............................................................................................................. 103

Table 68: CECONFIG Bit Definitions (CE RAM 0x20) ........................................................................... 103

Table 69: Sag Threshold, Phase Measurement, and Gain Adjust Control............................................. 105

Table 70: CE Transfer Variables (with Shunts)..................................................................................... 105

Table 71: CE Transfer Variables (with CTs) ......................................................................................... 105

Table 72: CE Energy Measurement Variables (with Shunts)................................................................. 106

Table 73: CE Energy Measurement Variables (with CTs) ..................................................................... 106

Table 74: Other Transfer Variables ...................................................................................................... 107

Table 75: CE Pulse Generation Parameters......................................................................................... 108

Table 76: CE Parameters for Noise Suppression and Code Version..................................................... 109

Table 77: CE Calibration Parameters................................................................................................... 110

Table 78: Absolute Maximum Ratings.................................................................................................. 113

Table 79: Recommended External Components .................................................................................. 114

Table 80: Recommended Operating Conditions................................................................................... 114

Table 81: Input Logic Levels ................................................................................................................ 115

Table 82: Output Logic Levels ............................................................................................................. 115

Table 83: Battery Monitor Performance Specifications (TEMP_BAT = 1) ............................................... 116

Table 84. Temperature Monitor............................................................................................................ 117

Table 85: Supply Current Performance Specifications.......................................................................... 118

Table 86: V3P3D Switch Performance Specifications........................................................................... 118

Table 87: 2.5 V Voltage Regulator Performance Specifications (VDD pin)............................................ 119

Table 88: Crystal Oscillator Performance Specifications....................................................................... 119

Table 89: PLL Performance Specifications........................................................................................... 120

Table 90: 71M6545/H VREF Performance Specifications..................................................................... 121

Table 91: ADC Converter Performance Specifications ......................................................................... 122

Table 92: Pre-Amplifier Performance Specifications............................................................................. 123

Table 93: Flash Memory Timing Specifications .................................................................................... 124

Table 94. SPI Slave Timing Specifications ........................................................................................... 124

Table 95: EEPROM Interface Timing ................................................................................................... 124

Table 96: RESET Pin Timing ............................................................................................................... 125

Table 97: RTC Range for Date ............................................................................................................ 125

Table 98: 71M6545/H Power and Ground Pins .................................................................................... 128

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