71M6545 Datasheet, PDF(32/134 Page) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

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71M6545 Datasheet, PDF (32/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

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Data Sheet 71M6545/H

PDS_6545_009

0000-13FF

2000-27FF

2800-287F

0000-00FF

Static RAM

Volatile

Non-volatile

(battery)

Volatile

External RAM

(XRAM)

Configuration

RAM (I/O RAM)

Configuration

RAM (I/O RAM)

Internal RAM

(on 1 KB boundary)

Shared by CE and

MPU

Hardware control

Battery-buffered

memory

Part of 80515 Core

5 KB

2 KB

128

256

MOVX Addressing

There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to

the external data RAM.

In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight

lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA

SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the

external data RAM.

In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.

This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no

additional instructions are needed to set up the eight high ordered bits of the address.

It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two

with direct access and two with paged access, to the entire 64 KB of external memory range.

Dual Data Pointer

The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that

is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called

DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS

selected when DPS[0] = 1.

The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers

are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected

DPTR for any activity.

The second data pointer may not be supported by certain compilers.

DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster

compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save and

restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.

By selecting the Evatronics R80515 core in the Keil compiler project settings and by using the compiler

directive âMODC2â, dual data pointers are enabled in certain library routines.

An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred

to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction

MOVX A,@Ri or MOVX @Ri,A.

Internal Data Memory Map and Access

The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory

address is always 1 byte wide. Table 10 shows the internal data memory map.

The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory

is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of

Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32

bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW, SFR

0xD0 ) select which bank is in use. The next 16 bytes form a block of bit addressable memory space

v1.0

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