71M6545 Datasheet, PDF (60/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
EECTRL Byte Written
Write -- With HiZ and WFR
SCLK (output)
CNT Cycles (6 shown)
SDATA (out/in)
SDATA output Z
D7
D6
D5
D4
D3
D2
(From 6520)
(LoZ)
BUSY
(From EEPROM)
(HiZ)
BUSY (bit)
Figure 19: 3-wire Interface. Write Command when HiZ=1 and WFR=1.
INT5
READY
2.5.12 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
and Configuration RAM (I/O RAM) locations. It is also able to send commands to the MPU. The interface
to the slave port consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins.
Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash
programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The
SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]).
Possible applications for the SPI interface are:
1) An external host reads data from CE locations to obtain metering information. This can be used in
applications where the 71M6545/H function as a smart front-end with preprocessing capability. Since the
addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but not
SFRs or the 80515-internal register bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory locations,
the external host can initiate and control processes in the 71M6545/H MPU. Writing to a CE or MPU
location normally generates an interrupt, a function that can be used to signal to the MPU that the
byte that had just been written by the external host must be read and processed. Data can also be
inserted by the external host without generating an interrupt.
3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the
71M6545/H as an analog front-end (AFE).
4) Flash programming by the external host (SPI Flash Mode).
SPI Transactions
A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state.
During this state, SPI_DO is held in high impedance state and all transitions on SPI_CLK and SPI_DI are
ignored. When SPI_CSZ falls, the port begins the transaction on the first rising edge of SPI_CLK. As
shown in Table 50, a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status
byte, followed by one or more bytes of data. The transaction ends when SPI_CSZ is raised. Some
transactions may consist of a command only.
When SPI_CSZ rises, SPI command bytes that are not of the form x0000000 cause the SPI_CMD (SFR
0xFD) register to be updated and then cause an interrupt to be issued to the MPU. The exception is if the
transaction was a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued.
SPI_CMD is not cleared when SPI_CSZ is high.
The SPI port supports data transfers up to 10 Mb/s. A serial read or write operation requires at least 8
clocks per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring that SPI
access to DRAM is always possible.
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