71M6545 Datasheet, PDF (50/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
Table 40: RTC Control Registers
Name
Location Rst Wk Dir Description
RTCA_ADJ[6:0] 2504[6:0] 40
RTC_P[16:14] 289B[2:0] 4
RTC_P[13:6] 289C[7:0] 0
RTC_P[5:0]
289D[7:2] 0
RTC_Q[1:0]
289D[1:0] 0
RTC_RD
2890[6] 0
RTC_WR
2890[7] 0
RTC_FAIL
2890[4] 0
RTC_SBSC[7:0] 2892[7:0]
-- R/W Register for analog RTC frequency adjustment.
4 R/W _{Registers for digital RTC adjustment.}
0
0
0x0FFBF ≤ RTC_P ≤ 0x10040
0 R/W Register for digital RTC adjustment.
Freezes the RTC shadow register so it is suitable for
0
R/W
MPU reads. When RTC_RD is read, it returns the
status of the shadow register: 0 = up to date, 1 =
frozen.
Freezes the RTC shadow register so it is suitable for
MPU write operations. When RTC_WR is cleared, the
contents of the shadow register are written to the RTC
0 R/W counter on the next RTC clock (~1 kHz). When
RTC_WR is read, it returns 1 as long as RTC_WR is
set, and continues to return one until the RTC counter
is updated.
Indicates that a count error has occurred in the RTC
0 R/W and that the time is not trustworthy. This bit can be
cleared by writing a 0.
R
Time remaining since the last 1 second boundary.
LSB = 1/128 second.
2.5.4.3 RTC Rate Control
The 71M6545/H has two rate adjustment mechanisms:
• The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register
RTCA_ADJ[6:0], that trims the crystal load capacitance.
• The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency
is processed in the RTC.
Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting
RTCA_ADJ[6:0] to 0x7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable
capacitance is approximately:
C _ADJ
=
RTCA _ ADJ
128
⋅16.5 pF
The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the
external crystal capacitors. The adjustment may occur at any time, and the resulting clock frequency should
be measured over a one-second interval.
The second rate adjustment is digital, and can be used to adjust the clock rate up to ±988ppm, with a
resolution of 3.8 ppm (±1.9 ppm). The rate adjustment is implemented starting at the next second-
boundary following the adjustment. Since the LSB results in an adjustment every four seconds, the
frequency should be measured over an interval that is a multiple of four seconds.
The clock rate is adjusted by writing the appropriate values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C,
0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]). Updates to RTC rate adjust registers, RTC_P and
RTC_Q, are done through the shadow register described above. The new values are loaded into the
counters when RTC_WR (I/O RAM 0x2890[7]) is lowered.
The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ∆ ppm,
RTC_P and RTC_Q are calculated using the following equation:
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