71M6545 Datasheet, PDF (129/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
Data Sheet 71M6545/H
6.8.2 71M6545/H Analog Pins
Table 99 lists the analog pins. Pin types: O = Output, I = Input. The circuit number denotes the
equivalent circuit, as specified in 6.8.4.
Table 99: 71M6545/H Analog Pins
Pin
No.
Name
Type Circuit
Description
57 IADC0
56 IADC1
44 IADC2
43 IADC3
42 IADC4
41 IADC5
40 ^IADC6
39 IADC7
Differential or single-ended Analog Line Current Sense Inputs:
These pins are voltage inputs to the internal A/D converter.
Typically, they are connected to the outputs of current
sensors. Unused pins must be tied to V3P3A.
When configured as differential inputs (i.e., by setting the
DIFFx_E control bits, where x=0, 2, 4, 6), pins are paired to form
differential inputs pairs: IADC0-IADC1, IADC2-IADC3, IADC4-
I
6 ^{IADC5, and IADC6-IADC7.}
IADC2-IADC3, IADC4-IADC5 and IADC6-IADC7 may be
configured for communication with the 71M6xx3 remote
isolated sensor interface (i.e., by setting the RMTx_E control
bits, where x=2, 4, 6). When configured as remote sensor
interfaces, these pins form balanced digital pairs for bi-
directional digital communications with a 71M6xx3 remote
isolated sensor.
54 VADC8 (VA)
53 ^{VADC9 (VB)}
I
52 ^{VADC10 (VC)}
Line Voltage Sense Inputs: These pins are voltage inputs to
6
the internal A/D converter. Typically, they are connected to
the outputs of resistor dividers. Unused pins must be tied to
V3P3A.
58 VREF
Voltage Reference for the ADC. This pin must be left
O
9 unconnected (floating). The VREF pin must be kept turned off
for normal operation (see VREF_CAL, I/O RAM 0x2704[7]).
48 XIN
49 XOUT
Crystal Inputs: A 32 kHz crystal should be connected across
these pins. Typically, a 15 pF capacitor is also connected
from XIN to GNDA and a 10 pF capacitor is connected from
I
O
8
XOUT to GNDA. It is important to minimize the capacitance
between these pins. See the crystal manufacturer datasheet for
details. If an external clock is used, a 150 mV (p-p) clock
signal should be applied to XIN, and XOUT should be left
unconnected.
v1.0
© 2008–2011 Teridian Semiconductor Corporation
129