71M6545 Datasheet, PDF (6/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
Tables
Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ......................................................... 15
Table 2. Required CE Code and Settings for CT Sensors ...................................................................... 16
Table 3: Multiplexer and ADC Configuration Bits................................................................................... 19
Table 4. RCMD[4:0] Bits ........................................................................................................................ 22
Table 5: Remote Interface Read Commands ........................................................................................ 23
Table 6: I/O RAM Control Bits for Isolated Sensor................................................................................. 23
Table 7: Inputs Selected in Multiplexer Cycles ....................................................................................... 26
Table 8: CKMPU Clock Frequencies...................................................................................................... 30
Table 9: Memory Map............................................................................................................................ 31
Table 10: Internal Data Memory Map ..................................................................................................... 33
Table 11: Special Function Register Map............................................................................................... 33
Table 12: Generic 80515 SFRs - Location and Reset Values ................................................................. 33
Table 13: PSW Bit Functions (SFR 0xD0) ............................................................................................... 35
Table 14: Port Registers (DIO0-14)........................................................................................................ 35
Table 15: Stretch Memory Cycle Width .................................................................................................. 36
Table 16: Baud Rate Generation............................................................................................................ 37
Table 17: UART Modes ......................................................................................................................... 37
Table 18: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 38
Table 19: PCON Register Bit Description (SFR 0x87) .............................................................................. 38
Table 20: Timers/Counters Mode Description ........................................................................................ 38
Table 21: Allowed Timer/Counter Mode Combinations........................................................................... 39
Table 22: TMOD Register Bit Description (SFR 0x89) ............................................................................ 39
Table 23: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 39
Table 24: The IEN0 Bit Functions (SFR 0xA8)........................................................................................ 40
Table 25: The IEN1 Bit Functions (SFR 0xB8)........................................................................................ 41
Table 26: The IEN2 Bit Functions (SFR 0x9A)........................................................................................ 41
Table 27: TCON Bit Functions (SFR 0x88) ............................................................................................. 41
Table 28: The T2CON Bit Functions (SFR 0xC8) ................................................................................... 41
Table 29: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 42
Table 30: External MPU Interrupts ......................................................................................................... 42
Table 31: Interrupt Enable and Flag Bits ................................................................................................ 43
Table 32: Interrupt Priority Level Groups................................................................................................ 43
Table 33: Interrupt Priority Levels .......................................................................................................... 44
Table 34: Interrupt Priority Registers (IP0 and IP1)................................................................................. 44
Table 35: Interrupt Polling Sequence ..................................................................................................... 44
Table 36: Interrupt Vectors .................................................................................................................... 44
Table 37: Flash Memory Access ............................................................................................................ 46
Table 38: Flash Security ........................................................................................................................ 47
Table 39: Clock System Summary ......................................................................................................... 49
Table 40: RTC Control Registers ........................................................................................................... 50
Table 41: I/O RAM Registers for RTC Temperature Compensation........................................................ 51
Table 42: I/O RAM Registers for RTC Interrupts .................................................................................... 52
Table 43: I/O RAM Registers for Temperature and Battery Measurement .............................................. 54
Table 44: Data/Direction Registers and Internal Resources for DIO0 to DIO14....................................... 55
Table 45: Data/Direction Registers for DIO19-25 and DIO28-29............................................................. 56
Table 46: Data/Direction Registers for DIO55 ........................................................................................ 56
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 56
Table 48: EECTRL Bits for 2-pin Interface............................................................................................... 57
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