71M6545 Datasheet, PDF (35/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
Data Sheet 71M6545/H
PSW Bit
7
6
5
Symbol
CV
AC
F0
Table 13: PSW Bit Functions (SFR 0xD0)
Function
Carry flag.
Auxiliary Carry flag for BCD operations.
General purpose Flag 0 available for user.
F0 is not to be confused with the F0 flag in the CESTATUS register.
4
RS1 Register bank select control bits. The contents of RS1 and RS0 select the
working register bank:
3
RS0
RS1/RS0
00
01
10
11
Bank selected
Bank 0
Bank 1
Bank 2
Bank 3
Location
0x00 – 0x07
0x08 – 0x0F
0x10 – 0x17
0x18 – 0x1F
2
OV Overflow flag.
1
–
User defined flag.
0
P
Parity flag, affected by hardware to indicate odd or even number of one bits in
the Accumulator, i.e. even parity.
Stack Pointer (SP, SFR 0x81):
The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer:
The data pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL (SFR 0x82) and DPL1 (SFR
0x84), respectively. The highest is DPH (SFR 0x83) and DPH1 (SFR 0x85), respectively. The data pointers
can be loaded as two registers (e.g. MOV DPL,#data8). They are generally used to access external code
or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter:
The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. This register is incremented
when fetching operation code or when operating on data from program memory.
Port Registers:
DIO0 through DIO14 are controlled by Special Function Registers P0, P1, P2, and P3 as shown in Table
14. Above DIO14, the DIOn[ ] registers in I/O RAM are used. Since the direction bits are contained in the
upper nibble of each SFR Pn register and the DIO bits are contained in the lower nibble, it is possible to
configure the direction of a given DIO pin and set its output value with a single write operation, thus
facilitating the implementation of bit-banged interfaces. Writing a 1 to a DIO_DIR bit configures the
corresponding DIO as an output, while writing a 0 configures it as an input. Writing a 1 to a DIO bit
causes the corresponding pin to be at high level (V3P3), while writing a 0 causes the corresponding pin to
be held at a low level (GND).
Table 14: Port Registers (DIO0-14)
SFR
Name
P0
P1
P2
P3
SFR
Address
80
90
A0
B0
D7 D6 D5 D4 D3 D2 D1 D0
DIO_DIR[3:0]
DIO_DIR[7:4]
DIO_DIR[11:8]
DIO_DIR[14:12]
DIO[3:0]
DIO[7:4]
DIO[11:8]
DIO[14:11]
All DIO ports on the chip are bi-directional. Each of them consists of a latch (SFR P0 to P3), an output
driver and an input buffer, therefore the MPU can output or read data through any of these ports. Even if
v1.0
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