71M6545 Datasheet, PDF (70/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
71M6545/H
Pulses
Samples
TMUX
Sag Warning
Data Ready
XFER_BUSY
XPULSE
YPULSE
VPULSE
WPULSE
CE_BUSY
MPU
Interrupt
PDS_6545_009
DIO1/interrupt
DIO2/interrupt
Host
MUX
CE
XRAM
SPI
Control
I/O RAM (Configuration RAM)
10/7/2010
Figure 22: Data Flow
In addition to the four pulse interrupts XPULSE, YPULSE, VPULSE, and WPULSE, the CE outputs two
interrupt signals: CE_BUSY and XFER_BUSY. XFER_BUSY signals the end of an accumulation interval
where data are ready for the host. This will occur whenever the CE has finished generating a sum by
completing an accumulation interval as determined by the number of samples given in SUM_SAMPS.
XFER_BUSY can be provided to the host via the test multiplexer output (TMUXOUT) to support
synchronization. The YPULSE output can be used to signal a sag event to the host.
Refer to 5.4 CE Interface Description on page 100 for additional information on setting up the device by
the host.
For several reasons, it is necessary to have a small MPU program in flash memory, even when the host
takes over all post-processing:
• The MPU has to be prevented from executing code. With the flash mostly empty, the MPU will
execute 0xFF op-codes until it runs into the CE code image. Executing the CE code image could
have undesired results, e.g., changes to core I/O RAM settings, and must therefore be avoided.
• The host cannot access the SFRs of the MPU directly. However, SFR access is required for
accessing the DIO pins. A small “driver” must exist to support SFR access, if the host needs to
control the DIO pins.
Sample MPU code that performs the tasks described above is available from Teridian.
During operation, the host needs to trigger the watchdog reset periodically in order to avoid watchdog
resets.
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