71M6545 Datasheet, PDF (57/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
MISSION
SLEEP
HIGH
HIGH-Z
LOW
V3P3SYS
V3P3D
DIO
Data Sheet 71M6545/H
MISSION
SLEEP
V3P3SYS
V3P3D
HIGH
HIGH-Z
LOW
DIO
GNDD
GNDD
Not recommended
Recommended
Figure 14: Connecting an External Load to DIO Pins
2.5.11 EEPROM Interface
The 71M6545/H provides hardware support for either a two-pin or a three-wire (µ-wire) type of EEPROM
interface. The interfaces use the EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E) registers for communication.
Two-pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is
multiplexed onto the DIO2 (SDCK) and DIO3 (SDATA) pins and is selected by setting DIO_EEX[1:0] = 01
(I/O RAM 0x2456[7:6]). The MPU communicates with the interface through the SFR registers EEDATA
and EECTRL. If the MPU wishes to write a byte of data to the EEPROM, it places the data in EEDATA and
then writes the Transmit code to EECTRL. This initiates the transmit operation which is finished when the
BUSY bit falls. INT5 is also asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if
the EEPROM acknowledged the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin
interface is selected are shown in Table 48.
Table 48: EECTRL Bits for 2-pin Interface
Status
Bit
Name
Read/
Write
Reset
State
Polarity
Description
7 ERROR
R
6 BUSY
R
5 RX_ACK R
4 TX_ACK R
0 Positive 1 when an illegal command is received.
0 Positive 1 when serial data bus is busy.
1 Positive 1 indicates that the EEPROM sent an ACK bit.
1
Positive
1 indicates when an ACK bit has been sent to the
EEPROM.
3:0 CMD[3:0] W
0000 Positive
CMD[3:0]
0000
0010
0011
0101
Operation
No-op command. Stops the I²C clock
(SDCK). If not issued, SDCK keeps
toggling.
Receive a byte from the EEPROM and
send ACK.
Transmit a byte to the EEPROM.
Issue a STOP sequence.
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