71M6545 Datasheet, PDF (42/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
Bit
Symbol
T2CON[4:0]
–
Not used.
Function
Bit
IRCON[7]
IRCON[6]
IRCON[5]
IRCON[4]
IRCON[3]
IRCON[2]
IRCON[1]
IRCON[0]
Table 29: The IRCON Bit Functions (SFR 0xC0)
Symbol
–
Not used
Function
–
Not used
IEX6
IEX5
IEX4
IEX3
IEX2
–
1 = External interrupt 6 occurred and has not been cleared.
1 = External interrupt 5 occurred and has not been cleared.
1 = External interrupt 4 occurred and has not been cleared.
1 = External interrupt 3 occurred and has not been cleared.
1 = External interrupt 2 occurred and has not been cleared.
Not used.
TF0 and TF1 (Timer 0 and Timer 1 overflow flags) is automatically cleared by hardware when the
service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in
other parts of the 71M6545/H, for example the CE, DIO, RTC, or EEPROM interface.
The external interrupts are connected as shown in Table 30. The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should
be programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that
interrupts 4 through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to
interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 30.
Table 30: External MPU Interrupts
External
Interrupt
0
1
2
3
4
5
6
Connection
Digital I/O
Digital I/O
CE_PULSE
CE_BUSY
VSTAT (VSTAT[2:0] changed)
EEPROM busy (falling), SPI (rising)
XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T
Polarity
rising
falling
rising
falling
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,
RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLLFALL have their own enable and flag bits in
addition to the interrupt 6, 4 and enable and flag bits (see Table 31: Interrupt Enable and Flag Bits).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.
The other flags, IE_XFER through IE_PB, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag is cleared unintentionally.
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