71M6545 Datasheet, PDF (61/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
Data Sheet 71M6545/H
Table 50: SPI Transaction Fields
Field
Name
Required
Size
(bytes)
Description
Address
Yes, except
single byte
transaction
2
16-bit address. The address field is not required if the transaction
is a simple SPI command.
Command
Yes
8-bit command. This byte can be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit. Unless
1
the transaction is multi-byte and SPI_CMD is exactly 0x80 or
0x00, the SPI_CMD register is updated and an SPI interrupt is
issued. Otherwise, the SPI_CMD register is unchanged and the
interrupt is not issued.
Status
Yes, if transaction
includes DATA
1
8-bit status field, indicating the status of the previous transaction.
This byte is also available in the MPU memory map as
SPI_STAT (I/O RAM 0x2708). See Table 52 for the contents.
Data
Yes, if transaction 1 or The read or write data. Address is auto incremented for each
includes DATA more new byte.
The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction
and the error status of the previous transaction. Potential error sources are:
• 71M6545/H not ready
• Transaction not ending on a byte boundary.
SPI Safe Mode
Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte
transfer region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use
the SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value,
single-byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in Figure 20, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
and a sequence of data bytes. A multi byte transaction is three or more bytes.
SERIAL READ
16 bit Address
8 bit CMD
Status Byte
DATA[ADDR]
DATA[ADDR+1]
(From Host) SPI_CSZ
(From Host) SPI_CK
(From Host) SPI_DI
(From 6545) SPI_DO
0
A15 A14
15 16
A1 A0 C7 C6 C5
HI Z
23 24
C0
ST7 ST6 ST5
31 32
x
ST0 D7 D6
Extended Read . . .
39 40
47
D1 D0 D7 D6
D1 D0
SERIAL WRITE
16 bit Address
8 bit CMD
Status Byte
DATA[ADDR]
DATA[ADDR+1]
(From Host) SPI_CSZ
0
(From Host) SPI_CK
15 16
23 24
31 32
Extended Write . . .
39 40
47
(From Host) SPI_DI x A15 A14
(From 6545) SPI_DO
A1 A0 C7 C6 C5
HI Z
C0
ST7 ST6 ST5
D7 D6
ST0
D1 D0 D7 D6
D1 D0 x
Figure 20: SPI Slave Port - Typical Multi-Byte Read and Write operations
v1.0
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