71M6545 Datasheet, PDF (43/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
Data Sheet 71M6545/H
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 31: Interrupt Enable and Flag Bits
Interrupt Enable
Name
Location
Interrupt Flag
Name
Location
Interrupt Description
EX0
EX1
EX2
EX3
EX4
EX5
EX6
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
SFR A8[[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
SFR B8[3]
SFR B8[4]
SFR B8[5]
2700[0]
2700[1]
2700[2]
2700[4]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
IE0
IE1
IEX2
IEX3
IEX4
IEX5
IEX6
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR 88[1]
SFR 88[3]
SFR C0[1]
SFR C0[2]
SFR C0[3]
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[4]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[4]
SFR F8[3]
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
RTC_1MIN interrupt (int 6)
RTC_T interrupt (int 6)
SPI interrupt
EEPROM interrupt
CE_Xpulse interrupt (int 2)
CE_Ypulse interrupt (int 2)
CE_Wpulse interrupt (int 2)
CE_Vpulse interrupt (int 2)
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32.
Group
0
1
2
3
4
5
Table 32: Interrupt Priority Level Groups
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
–
Group Members
Serial channel 1 interrupt
–
–
External interrupt 2
–
External interrupt 3
–
External interrupt 4
–
External interrupt 5
–
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 33) by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in
IP1(SFR 0xB9) (Table 34). If requests of the same priority level are received simultaneously, an internal
polling sequence as shown in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
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