71M6545 Datasheet, PDF(67/134 Page) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

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71M6545 Datasheet, PDF (67/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

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PDS_6545_009

Data Sheet 71M6545/H

3.2 SLP Mode (Sleep Mode)

Shortly after system power (V3P3SYS) is applied, the part will be in mission mode (MSN mode). MSN

mode means that the part is operating with system power and that the internal PLL is stable. This mode

is the normal operation mode where the part is capable of measuring energy.

When system power is not available, the 71M6545/H will be in SLP mode, if a battery is attached to the

VBAT_RTC pin.

Shortly after system power is removed (V3P3SYS < 3.0 VDC), VSTAT[2:0] will assume the value 001,

issuing a warning to the MPU. The IC can still operate in this state, however, the analog functions are not

considered accurate. Assuming that the recommended MPU setup code is resident in flash memory (see

2.4.1 MPU Setup Code on page 30), at V3P3SYS < 2.8 VDC, the 71M6545/H will be forced to SLP mode

by the MPU setting the SLEEP bit (I/O RAM 0x28B2[7]).

When system power is restored, the 71M6545/H will automatically transition from SLP mode back to MSN

mode.

Table 55: Available Circuit Functions

Circuit Function

System Power Battery Power

MSN

SLP

Yes

FIR

Yes

ADC, VREF

Yes

PLL

Yes

Battery measurement

Yes

Temperature sensor

Yes

Maximum MPU clock rate

4.92MHz

(from PLL)

MPU_DIV clock divider

Yes

ICE

Yes

DIO Pins

Yes

Watchdog Timer

Yes

V3P3D Pin

Yes

VDD Pin

Yes

EEPROM Interface (2-wire)

Yes

EEPROM Interface (3-wire)

Yes

UART (full speed)

Yes

SPI slave port

Yes

SPI Special Flash Mode

Yes

Optical TX modulation

Yes

Flash Read

Yes

Flash Page Erase

Yes

Flash Write

Yes

RAM Read and Write

Yes

OSC and RTC

Yes

RAM data preservation

Yes

NV RAM data preservation

Yes

â indicates not active

The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the

SLEEP bit. The purpose of the SLP mode is to consume the least power while still maintaining the RTC,

temperature compensation of the RTC, and the non-volatile portions of the I/O RAM.

In SLP mode, the V3P3D pin is disconnected, removing all sources of leakage from V3P3SYS. The non-

volatile memory domain and the basic functions, such as temperature sensor, oscillator, and RTC, are

preserved and RTC and oscillator continue to run. This mode can be exited only by system power up.

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