71M6545 Datasheet, PDF (48/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
2.5.1.2 MPU/CE RAM
The 71M6545/H includes 5 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in
the MPU core. The 5KB of static RAM are used for data storage by both MPU and CE and for the
communication between MPU and CE.
2.5.1.3 I/O RAM (Configuration RAM)
The I/O RAM can be seen as a series of hardware registers that control basic hardware functions. I/O
RAM address space starts at 0x2000. The registers of the I/O RAM are listed in Table 59.
The 71M6545/H includes 128 bytes non-volatile RAM memory on-chip in the I/O RAM address space
(addresses 0x2800 to 0x287F). This memory section is supported by the voltage applied at VBAT_RTC,
and the data in it are preserved in SLP mode provided that the voltage at the VBAT_RTC pin is within
specification.
2.5.2 Oscillator
The 71M6545/H oscillator drives a standard 32.768 kHz watch crystal. This type of crystal is accurate and
does not require a high-current oscillator circuit. The oscillator has been designed specifically to handle
watch crystals and is compatible with their high impedance and limited power handling capability. The
oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to 2.5.4, Real-Time
Clock (RTC) for more information.
The oscillator is powered from the V3P3SYS pin or from the VBAT_RTC pin, depending on the V3OK
internal bit (i.e., V3OK = 1 if V3P3SYS ≥ 2.8 VDC and V3OK = 0 if V3P3SYS < 2.8 VDC). The oscillator
requires approximately 100 nA, which is negligible compared to the internal leakage of a battery.
If VBAT_RTC is connected to a drained battery or disconnected, a battery test that sets
TEMP_BAT may drain the supply connected to VBAT_RTC and cause the oscillator to stop. A
stopped oscillator may force the device to reset. Therefore, an unexpected reset during a battery
test should be interpreted as a battery failure.
2.5.3 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output that is multiplied by a PLL by
600 to obtain 19.660800 MHz, the master clock (MCK). All on-chip timing, except for the RTC clock, is
derived from MCK. Table 39 provides a summary of the clock functions and their controls.
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see 2.4.8
Timers and Counters).
The master clock can be boosted to 19.66 MHz by setting the PLL_FAST bit = 1 (I/O RAM 0x2200[4]) and
can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CKMPU is determined by
another divider controlled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) and can be
set to MCK*2^-(MPU_DIV+2) where MPU_DIV[2:0] may vary from 0 to 4. When the ICE_E pin is high, the
circuit also generates the 9.83 MHz clock for use by the emulator.
When the part is waking up from SLP mode, the PLL is turned on in 6.29 MHz mode, and the PLL
frequency is not be accurate until the PLL_OK (SFR 0xF9[4]) flag rises. Due to potential overshoot, the MPU
should not change the value of PLL_FAST until PLL_OK is true.
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