71M6545 Datasheet, PDF (68/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
If the SLEEP bit is asserted when system power is present, the 71M6545/H will still enter SLP mode. It
will drop WAKE, and then will begin the standard wake from sleep procedure.
After the transition from SLP mode to MSN mode the PC will be at 0x0000, the XRAM is in an undefined
state, and the I/O RAM is only partially preserved (see the description of I/O RAM states in 5.2). The non-
volatile sections of the I/O RAM are preserved unless RESET goes high.
The 71M6545/H features a temperature sensor and automatic digital temperature compensation circuitry
that can operate from a battery connected to the VBAT_RTC pin, in the event of ac power loss. When ac
power loss occurs, the 71M6545/H crystal oscillator, temperature sensor and digital temperature
compensation circuitry automatically obtain power from the VBAT_RTC pin. See 2.5.4 Real-Time Clock
(RTC) on page 49.
3.3 Fault and Reset Behavior
3.3.1 Events at Power-Down
Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and
also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be
tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A
pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage. The following
discussion assumes that the V3P3A and V3P3SYS pins are tied together at the PCB level.
During a power failure, as V3P3A falls, two thresholds are detected:
• The first threshold, at 3.0 VDC (VSTAT[2:0] = 001, SFR 0xF9[2:0]), warns the MPU that the analog
modules are no longer accurate. Other than warning the MPU, the hardware takes no action when
this threshold is crossed. This comparison produces an internal bit named V3OKA.
• The second threshold, at 2.8 VDC, causes the 71M6545/H to switch to battery power. This switching
happens while the FLASH and RAM systems are still able to read and write. This comparison
produces an internal bit named V3OK.
The power quality is reflected by the VSTAT[2:0] register in I/O RAM space, as shown in Table 56. The
VSTAT[2:0] register is located at SFR address F9 and occupies bits 2:0. The VSTAT[2:0] field can only be
read.
In addition to the state of the main power, the VSTAT[2:0] register provides information about the internal
VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the 71M6545/H
always switches from battery to system power.
Table 56: VSTAT[2:0] (SFR 0xF9[2:0])
VSTAT[2:0]
000
001
010
011
101
Description
System Power OK. V3P3A > 3.0 VDC. Analog modules are functional and accurate.
System Power is low. 2.8 VDC < V3P3A < 3.0 VDC. Analog modules not accurate.
VDD is OK. VDD > 2.25 VDC. The IC has full digital functionality.
2.25 VDC > VDD > 2.0 VDC. Flash write operations are inhibited.
VDD < 2.0, which means that the MPU is nearly out of voltage. A reset occurs in 4
cycles of the crystal clock CK32.
The response to a system power fault is almost entirely controlled by firmware. During a power failure,
system power slowly falls. An interrupt notifies the MPU whenever VSTAT[2:0] changes. It is the MPU’s
responsibility to reduce power, when necessary, by slowing the clock rate, disabling the PLL, etc.
Precision analog components such as the bandgap reference, the bandgap buffer, and the ADC are
powered only by the V3P3A pin and become inaccurate and ultimately unavailable as the V3P3A pin
voltage continues to drop (i.e., circuits powered by the V3P3A pin are not backed by the VBAT_RTC
pin). When the V3P3A pin falls below 2.8 VDC, the ADC clocks are halted and the amplifiers are
unbiased. Meanwhile, control bits such as ADC_E bit (I/O RAM 0x2704[4]) are not affected, since their I/O
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