71M6545 Datasheet, PDF (58/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
Status
Bit
Name
Read/
Write
Reset
State
Polarity
Description
0110
1001
Others
Receive the last byte from the
EEPROM and do not send ACK.
Issue a START sequence.
No operation, set the ERROR bit.
The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The
direction of the DIO line can be changed from input to output and an output value can be written
with a single write operation, thus avoiding collisions (see Table 14 Port Registers (DIO0-14)).
Therefore, no resistor is required in series SDATA to protect against collisions.
Three-Wire (µ-Wire) EEPROM Interface with Single Data Pin
A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is
selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are
shown in Table 49. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM
or read from the EEPROM, depending on the values of the EECTRL bits.
Three-Wire (µ-Wire/SPI) EEPROM Interface with Separate Di/DO Pins
If DIO_EEX[1:0] = 11, the 71M6545/H three-wire interface is the same as above, except DI and DO are
separate pins. In this case, DIO3 becomes DO and DIO8 becomes DI. The timing diagrams are the
same as for DIO_EEX[1:0] = 10 except that all output data appears on DO and all input data is expected
on DI. In this mode, DI is ignored while data is being received on DO. This mode is compatible with SPI
modes 0,0 and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on the rising
edge of the clock.
Table 49: EECTRL Bits for the 3-wire Interface
Control
Bit
7
6
5
4
3:0
Name
Read/
Write
WFR
W
BUSY
R
HiZ
W
RD
W
CNT[3:0] W
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY is delayed until
a rising edge is seen on the data line. This bit can be used during the
last byte of a Write command to cause the INT5 interrupt to occur when
the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ=0.
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immediately
after the last SDCK rising edge.
Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD = 1, CNT bits of data are read MSB first, and right
justified into the low order bits of EEDATA. If RD = 0, CNT bits are sent
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA simply obeys the HiZ bit.
The timing diagrams in Figure 15 through Figure 19 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 15 through Figure 19
are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
drives SDATA, but transitions to HiZ (high impedance) when CS falls. The firmware should then
58
© 2008–2011 Teridian Semiconductor Corporation
v1.0