71M6545 Datasheet, PDF (69/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
Data Sheet 71M6545/H
RAM storage is powered from the VDD pin (2.5 VDC). The VDD pin is supplied with power through an
internal 2.5 VDC regulator that is connected to the V3P3D pin. Note that the V3P3SYS and V3P3A pins
are typically tied together at the PCB level.
3.3.2 Reset Sequence
When the RESET pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator
and RTC. Additionally, all I/O RAM bits are forced to their RST state. A reliable reset does not occur until
RESET has been high at least for 2 µs. Note that TMUX and the RTC are not reset unless the TEST pin
is pulled high while RESET is high.
The RESET control bit (I/O RAM 0x 2200[3]) performs an identical reset to the RESET pin except that a
significantly shorter reset timer is used.
Once initiated, the reset sequence waits until the reset timer times out. The time out occurs in 4100
CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences from
address 0x0000. See 2.5.1.1 for a detailed description of the pre-boot and boot sequences.
A softer form of reset is initiated when the E_RST pin of the ICE interface is pulled low. This event causes
the MPU and other registers in the MPU core to be reset but does not reset the remainder of the
71M6545/H. It does not trigger the reset sequence. This type of reset is intended to reset the MPU
program, but not to make other changes to the chip’s state.
3.4 Data Flow and Host Communication
The data flow between the Compute Engine (CE) and the host is shown in Figure 22. In a typical
application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IADC0-
IADC1, VADC8 (VA), IADC2-IADC3, etc., performing calculations to measure active power (Wh),
reactive power (VARh), A²h, and V²h for four-quadrant metering. These measurements are then
accessed by the host via the SPI interface, processed further and stored and/or displayed. For example,
to obtain the RMS current value in phase A, the host reads the I0SQSUM_X register of the CE, scales it
with VMAX, IMAX, and the LSB, as given in the CE Interface description (see 5.4 CE Interface
Description on page 100), and then performs a square-root operation. Similarly, momentary real power
and reactive power available via the WSUM_X and VARSUM_X registers only have to be scaled by the
host, while the apparent power has to be post-processed as follows:
S = P² + Q²
Figure 22 illustrates the CE-to-host data flow.
v1.0
© 2008–2011 Teridian Semiconductor Corporation
69