71M6545 Datasheet, PDF (104/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
CECONFIG
bit
23
Name
Reserved
Default
0
22
EXT_TEMP
0
21
EDGE_INT
1
20
SAG_INT
1
19:8
SAG_CNT
218
(0xDA)
7:6
FREQSEL[1:0] 0
5
EXT_PULSE 1
4:2
Reserved
0
1
PULSE_FAST 0
0
PULSE_SLOW 0
Description
Reserved.
When 1, the MPU controls temperature compensation via the
GAIN_ADJn (CE RAM 0x40-0x42), when 0, the CE is in control.
When 1, XPULSE produces a pulse for each zero-crossing of
the mains phase selected by FREQSEL[1:0] , which can be used
to interrupt the MPU.
When 1, activates the YPULSE/DIO7 output when a sag is
detected on the phase selected with FREQSEL[1:0].
The number of consecutive voltage samples below SAG_THR
(CE RAM 0x24) before a sag alarm is declared. The default value
is equivalent to 100 ms.
FREQSEL[1:0] selects the phase to be used for the frequency
monitor, sag detection, the phase-to-phase lag calculation and
for the zero crossing counter (MAINEDGE_X, CE RAM 0x83).
FREQ SEL[1:0]
0
0
0
1
1
0
1
1
Phase
Selected
A
B
C
Phases Selected
PH_AtoB_X PH_AtoC_X
A-B
A-C
B-C
B-A
C-A
C-B
Not allowed
When zero, causes the pulse generators to respond to internal
data. WPULSE = WSUM_X (CE RAM 0x84), VPULSE = VARSUM_X
(CE RAM 0x88.) Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER (CE RAM 0x44 and 0x48)
Reserved.
When PULSE_FAST = 1, the pulse generator input is increased
16x. When PULSE_SLOW = 1, the pulse generator input is
reduced by a factor of 64. These two parameters control the
pulse gain factor X (see table below). Allowed values are either
1 or 0. Default is 0 for both (X = 6).
PULSE_FAST PULSE_SLOW
0
0
0
1
1
0
1
1
X
1.5 * 2² = 6
1.5 * 2^-4 = 0.09375
1.5 * 2⁶ = 96
Do not use
The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag
interrupt. Thus, a SAG_INT event occurs when the selected phase has satisfied the sag event criteria as
set by the SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]).
When the SAG_INT bit (CE RAM 0x20[20]) is set to 1, a sag event generates a transition on the YPULSE
output. After a sag interrupt, the MPU should change the FREQSEL[1:0] setting to select the other phase,
if it is powered. Even though a sag interrupt is only generated on the selected phase, all three phases
are simultaneously checked for sag. The presence of power on a given phase can be sensed by directly
checking the SAG_A, SAG_B and SAG_C bits in CESTATUS (CE RAM 0x80[0:1]).
The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE)
temperature compensation is enabled.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the pulse rate (external
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