71M6545 Datasheet, PDF (38/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

Data Sheet 71M6545/H
PDS_6545_009
The proper way to clear these flag bits is to write a byte mask consisting of all ones except
for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to
ignore ones written to them.
Bit
S0CON[7]
S0CON[6]
S0CON[5]
S0CON[4]
S0CON[3]
S0CON[2]
S0CON[1]
S0CON[0]
Table 18: The S0CON (UART0) Register (SFR 0x98)
Symbol
SM0
Function
The SM0 and SM1 bits set the UART0 mode:
Mode
Description
SM0
SM1
0
N/A
0
0
1
8-bit UART
0
1
SM1
2
9-bit UART
1
0
3
9-bit UART
1
1
SM20
REN0
TB80
RB80
TI0
RI0
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9^th data bit received. In Mode 1, SM20 is 0, RB80 is the
stop bit. In mode 0, this bit is not used. Must be cleared by software.
Transmit interrupt flag; set by hardware after completion of a serial transfer. Must
be cleared by software (see Caution above).
Receive interrupt flag; set by hardware after completion of a serial reception. Must
be cleared by software (see Caution above).
Bit
PCON[7]
Table 19: PCON Register Bit Description (SFR 0x87)
Symbol
SMOD
Function
The SMOD bit doubles the baud rate when set
2.4.8 Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured
for counter or timer operations.
In timer mode, the register is incremented every machine cycle, i.e., it counts up once for every 12 periods of
the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the
corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock
frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper recognition of the
0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 20 and Table 21. The
TMOD (SFR 0x89) register, shown in
Table 22, is used to select the appropriate mode. The timer/counter operation is controlled by the TCON
(SFR 0x88) register, which is shown in Table 23. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON
register start their associated timers when set.
Table 20: Timers/Counters Mode Description
M1
M0
Mode
Function
0
0
Mode 0 13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 (SFR
0x8A or SFR 0x8B) register and the remaining 8 bits in the TH0 or TH1
(SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively).
The 3 high order bits of TL0 and TL1 are held at zero.
0
1
Mode 1 16-bit Counter/Timer mode.
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