71M6545 Datasheet, PDF (37/134 Pages) Maxim Integrated Products – Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size

PDS_6545_009
Data Sheet 71M6545/H
WDCON[7] (SFR 0xD8) selects whether timer 1 or the internal baud rate generator is used. All UART
transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for
variable communication baud rates from 300 to 38400 bps. Table 16 shows how the baud rates are
calculated. Table 17 shows the selectable UART operation modes.
Table 16: Baud Rate Generation
UART0
UART1
Using Timer 1
(WDCON[7] = 0)
2^smod * f_CKMPU/ (384 * (256-TH1))
N/A
Using Internal Baud Rate Generator
(WDCON[7] = 1)
2^smod * f_CKMPU/(64 * (2¹⁰-S0REL))
f_CKMPU/(32 * (2¹⁰-S1REL))
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.
(S0RELL, S0RELH, S1RELL, S1RELH are SFR 0xAA, SFR 0xBA, SFR 0x9D and SFR 0xBB, respectively) SMOD
is the SMOD bit in the SFR PCON register (SFR 0x87). TH1 (SFR 0x8D) is the high byte of timer 1.
Mode 0
Mode 1
Mode 2
Mode 3
Table 17: UART Modes
UART 0
UART 1
N/A
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of f_CKMPU
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud rate
generator or timer 1)
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
N/A
N/A
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant 1.
8-bit serial modes with parity can be simulated by setting and reading the 9^th bit, using the control
bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B) registers
for transmit and RB81 (S1CON[2]) for receive operations.
All supported operation modes use oversampling for the incoming bit stream when receiving data. Each
bit is sampled three times at the projected middle of the bit duration. This technique allows for deviations
of the received baud rate from nominal of up to 3.5%.
The feature of receiving 9 bits (Mode 3 for UART0) can be used as handshake signals for inter-processor
communication in multi-processor systems. In this case, the slave processors have bit SM20 (S0CON[5])
for UART0, set to 1. When the master processor outputs the slave’s address, it sets the 9^th bit to 1, causing a
serial port receive interrupt in all the slaves. The slave processors compare the received byte with their
address. If there is a match, the addressed slave clears SM20 or SM21 and receive the rest of the message.
The rest of the slaves ignore the message. After addressing the slave, the host outputs the rest of the
message with the 9^th bit set to 0, so no additional serial port receive interrupts is generated.
UART Control Registers:
The functions of UART0 depend on the setting of the Serial Port Control Register S0CON shown in Table
18, and the PCON register shown in Table 19.
Since the TI0 and RI0 bits are in an SFR bit addressable byte, common practice would be to
clear them with a bit operation, but this must be avoided. The hardware implements bit
operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after the
read, but before the write, its flag is cleared unintentionally.
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