UPI-452 Datasheet, PDF (9/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
UPI-452 PIN DESCRIPTIONS (Continued)
Symbol
Pin
Type
Name and Function
Port 4
P4 0
1
2
3
4
5
6
7
I O Port 4 is an 8-bit quasi-bi-directional I O port Port 4 can sink
30
source four TTL inputs
32
33
34
35
36
37
RST
20
I
A high level on this pin for two machine cycles while the oscillator is
running resets the device An internal pulldown resistor permits
Power-on reset using only a capacitor connected to V_CC
This pin does not receive the power down voltage as is the case for
HMOS MCS-51 family members This function has been transferred
to the V_CC pin
ALE
18
O Provides Address Latch Enable output used for latching the
address into external memory during normal operation ALE can
sink source eight LS TTL inputs
PSEN
19
O The Program Store Enable output is a control signal that enables
the external Program Memory to the bus during normal fetch
operation PSEN can sink source eight LS TTL inputs
EA
17
I
When held at TTL high level the UPI-452 executes instructions
from the internal ROM when the PC is less than 8192 (8K 2000H)
When held at a TTL low level the UPI-452 fetches all instructions
from external Program Memory
DB0
58
I O Host Bus Interface is an 8-bit bi-directional bus It is used to transfer
DB1
57
data and commands between the UPI-452 and the host processor
DB2
56
This bus can sink source eight LS TTL inputs
DB3
55
DB4
54
DB5
53
DB6
52
DB7
51
CS
44
I
This pin is the Chip Select of the UPI-452
A0
40
I
These three address lines are used to interface with the host
A1
41
system They define the UPI-452 operations The interface is
A2
42
compatible with the Intel microprocessors and the MULTIBUS
READ
46
I
This pin is the read strobe from the host CPU Activating this pin
causes the UPI-452 to place the contents of the Output FIFO (either
a command or data) or the Host Status Control Special Function
Register on the Slave Data Bus
WRITE
47
I
This pin is the write strobe from the host Activating this pin will
cause the value on the Slave Data Bus to be written into the register
specified by A0 – A2
DRQIN
INTRQIN
49
O This pin requests an input transfer from the host system whenever
the Input Channel requires data
DRQOUT
48
INTRQOUT
O This output pin requests an output transfer whenever the Output
Channel requires service If the external host to UPI-452 DMA is
enabled and a Data Stream Command is at the Output FIFO
DRQOUT is deactivated and INTRQ is activated (see ‘GENERAL
PURPOSE DMA CHANNELS’ section)
9