UPI-452 Datasheet, PDF (24/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
DMA Requests to the Host
The UPI-452 generates two DMA requests DRQIN
and DRQOUT to facilitate data transfer between the
Host and the Input and Output FIFO channels A
DMA acknowledge DACK is used as a chip select
and initiates a data transfer The external READ and
WRITE signals select the Input and Output FIFO re-
spectively The CS and address lines can also be
used as a DMA acknowledge for processors with
onboard DMA controllers which do not generate a
DACK signal
The internal CPU can configure the UPI-452 to re-
quest service from the external host via DMA or in-
terrupts by programming Mode SFR MD6 bit In ad-
dition the external Host enables DMA requests
through bits 6 and 7 of the Host Control SFR When
a DMA request is invoked the number of bytes trans-
ferred to the Input FIFO is the total number of bytes
in the Input FIFO (as determined by the CBP SFR)
minus the value programmed in the Input FIFO
Threshold SFR The DMA request line is activated
only when the Input FIFO has a threshold number of
bytes that can be transferred
The Output FIFO DMA request is activated when a
DSC is written by the internal CPU at the end of a
less than threshold size block of data (Flush Mode)
or when the Output FIFO threshold is reached The
request remains active until the Input FIFO becomes
full or the Output FIFO becomes empty If a DSC is
encountered during an Output FIFO DMA transfer
the DMA request is dropped until the DSC is read
The DMA request will be reactivated after the DSC is
read and remains active until the Output FIFO be-
comes empty or another DSC is encountered
FIFO MODULE - INTERNAL CPU
INTERFACE
Overview
The Input and Output FIFOs are accessed by the
internal CPU through direct addressing of the FIFO
IN COMMAND IN and FIFO OUT COMMAND OUT
Special Function Registers All of the 80C51 instruc-
tions involving direct addressing may be used to ac-
cess the FIFO’s SFRs The FIFO IN COMMAND IN
and Immediate Command In SFRs are actually read
only registers and their Output counterparts are
write only Internal DMA transfers data between In-
ternal memory External Memory and the Special
Function Registers The Special Function Registers
appear as another group of dedicated memory ad-
dresses and are programmed as the source or desti-
nation via the DMA0 DMA1 Source Address or Des-
tination Address Special Function Registers The
FIFO module manages the transfer of data between
the external host and FIFO SFRs
Internal CPU Access to FIFO Via
Software Instructions
The internal CPU has access to the Input and Out-
put FIFOs via the FIFO IN COMMAND IN and FIFO
OUT COMMAND OUT SFRs which reside in the
Special Function Register Array At the end of every
instruction that involves a read of the FIFO IN COM-
MAND IN SFR the SFR is written over by a new
byte from the Input FIFO channel when available At
the end of every instruction that involves a write to
the FIFO OUT COMMAND OUT SFR the new byte
is written into the Output FIFO channel and the write
pointer is incremented after the write operation (post
incremented)
The internal CPU reads the Input FIFO by using the
FIFO IN COMMAND IN SFR as the source register
in an instruction Those instructions which read the
Input FIFO are listed below
ADD A FIFO IN COMMAND IN
ADDC A FIFO IN COMMAND IN
PUSH FIFO IN COMMAND IN
ANL A FIFO IN COMMAND IN
ORL A FIFO IN COMMAND IN
XRL A FIFO IN COMMAND IN
CJNE A FIFO IN COMMAND IN rel
SUBB A FIFO IN COMMAND IN
MOV direct FIFO IN COMMAND IN
MOV Ri FIFO IN COMMAND IN
MOV Rn FIFO IN COMMAND IN
MOV A FIFO IN COMMAND IN
After each access to these registers they are over-
written by a new byte from the FIFO
NOTE
Instructions which use the FIFO IN or COMMAND
IN SFR as both a source and destination register
will have the data destroyed as the next data byte
is rewritten into the FIFO IN register at the end of
the instruction These instructions are not support-
ed by the UPI-452 FIFO Data can only be read
through the FIFO IN SFR and DSCs through the
COMMAND IN SFR Data read through the COM-
MAND IN SFR will be read as 0FFH and DSCs
read through the FIFO IN SFR will be read as
OFFH The Immediate Command in SFR is read
with the same instructions as the FIFO IN and
COMMAND IN SFRs
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