UPI-452 Datasheet, PDF (12/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
FIFO Read Write Pointers
These normally operate in auto-increment (and auto-
rollover) mode but can be reassigned by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-Ex-
ternal Host Interface FIFO DMA Freeze Mode de-
scription)
Threshold Register
The Input FIFO Threshold SFR contains the number
of empty bytes that must be available in the Input
FIFO to generate a Host interrupt The Output FIFO
Threshold SFR contains the number of bytes data
and or DSC(s) that must be in the FIFO before an
interrupt is generated The Threshold feature pre-
vents the Host from being interrupted each time the
FIFO needs to load or unload one byte of data The
thresholds therefore allow the FIFO’s operation to
be adjusted to the speed of the Host optimizing the
overall interface performance
NOTE
DSC’s should be allowed to be written into the out-
put FIFO by the UPI-452 code only when the serv-
ice request is law The service request can be mon-
itored by b7 of OTHR This guideline will elimate
the possibility of a DSC being written to the output
FIFO with the intention of setting the service re-
quest while having the number of bytes in the out-
put FIFO below the threshold This condition can
occur if the FIFO contains at least two bytes the
service request is being asserted and the host
reads from the output FIFO until one byte remains
Immediate Commands
The UPI-452 provides in addition to data and DSCs
a third direct means of communication between the
external Host and internal CPU called Immediate
Commands As the name implies an Immediate
Command is available to the receiving CPU immedi-
ately via an interrupt without being entered into the
FIFO as are Data Stream Commands Like Data
Stream Commands Immediate Commands are writ-
ten either via a unique external address by the host
CPU or via dedicated SFR by the internal CPU
The DSC and or Immediate Command interface
may be defined as either Interrupt or Polled under
user program control via the Interrupt Enable (IE)
Slave Control Register (SLCON) and Interrupt En-
able Priority (IEP) Special Function Registers for the
internal CPU and via the Host Control SFR for the
external Host CPU
DMA
The UPI-452 contains a two channel internal DMA
controller which allows transfer of data between any
of the three writeable memory spaces Internal Data
Memory External Load Expansion Bus Data Memo-
ry and the Special Function Register array The Spe-
cial Function Register array appears as a set of
unique dedicated memory addresses which may be
used as either the source or destination address of a
DMA transfer Each DMA channel is independently
programmable via dedicated Special Function Reg-
isters for mode source and destination addresses
and byte count to be transferred Each DMA channel
has four programmable modes
Alternate Cycle Mode
Burst Mode
FIFO or Serial Channel Demand Mode
External Demand Mode
A complete description of each mode and DMA op-
eration may be found in the section titled ‘‘General
Purpose DMA Channels’’
FIFO SLAVE INTERFACE
FUNCTIONAL DESCRIPTION
Overview
The FIFO is a 128 Byte RAM array with recirculating
pointers to manage the read and write accesses
The FIFO consists of an Input and an Output chan-
nel Access cycles to the FIFO by the internal CPU
and external Host are interleaved and appear to be
occurring concurrently to both the internal CPU and
external Host Interleaving access cycles ensures
efficient use of this shared resource The internal
CPU accesses the FIFO in the same way it would
access any of the Special Function Registers e g
direct and register indirect addressing as well as ar-
ithmetric and logical instructions
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