UPI-452 Datasheet, PDF (19/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Symbolic
Address
SLCON
IFI
OFI ICII ICOI FRZ
(MSB)
Status On Reset
0
0
0
0
0
1
IFRS
0
OFRS
(LSB)
0
Physical
Address
0E8H
IFI
OFI
ICII
ICOI
FRZ
SC2
IFRS
OFRS
Enable Input FIFO Interrupt (due to Underrun Error Condition Data Stream Command or Request
Service)
1 ^e Enable
0 ^e Disable
Enable Output FIFO Interrupt (due to Overrun Error Condition or Request Service)
1 ^e Enable
0 ^e Disable
Note If the DMA is configured to service a FIFO demand then the Request for Service Interrupt is
not generated
Generate Interrupt when a command is written to the Immediate Command in Register
1 ^e Enable
0 ^e Disable
Generate Interrupt when Immediate Command Out Register is Available
1 ^e Enable
0 ^e Disable
Enable FIFO DMA Freeze Mode
1 ^e Normal operation
0 ^e FIFO DMA Freeze Mode
(reserved)
Input FIFO Channel Request for Service
1 ^e Request when Input FIFO not empty
0 ^e Request when Input FIFO full
Output FIFO Channel Request for Service
1 ^e Request when Output FIFO not full
0 ^e Channel Request when Output FIFO empty
NOTES
A ‘1’ will be read from all SFR reserved locations except HCON SFR HC0 and HC2
‘reserved’ these locations are reserved for future use by Intel Corporation
3) Slave Status SFR (SSTAT)
The bits in the Slave Status SFR reflect the status of the FIFO-internal CPU interface It can be read during an
internal interrupt service routine to determine the nature of the interrupt or read during a polling sequence to
determine a course of action
Symbolic
Physical
Address
Address
SSTAT
SST7 SST6 SST5 SST4 SST3 SST2 SST1 SST0
0E9H
w x Output FIFO Status
Status On Reset
w Input FIFO Status x
1
0
0
0
1
1
1
1
(MSB)
(LSB)
19