UPI-452 Datasheet, PDF (34/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Interrupt Priority SFR (IP)
A priority level of 0 or 1 may be assigned to each interrupt source with 1 being higher priority level through the
IP and the IEP (Interrupt Enable and Priority) SFR A priority level of 1 interrupt can interrupt a priority level 0
service routine to allow nesting of interrupts
Symbolic
Address
IP
Symbol
(MSB)
Position
IP 7
IP 6
IP 5
PS
IP 4
PT1
IP 3
PX1
IP 2
PT0
IP 1
PX0
IP 0
PS PT1 PX1 PT0
Function
(reserved)
(reserved)
(reserved)
Local Serial Channel
Internal Timer Counter 1
External Interrupt Request 1
Internal Timer Counter 0
External Interrupt Request 0
PX0
(LSB)
Physical
Address
0B8H
Priority Within
A Level
(lowest)
07
05
03
01
00
(highest)
Interrupt Enable and Priority SFR (IEP)
The Interrupt Enable and Priority Register establishes the enabling and priority of those resources not covered
in the Interrupt Enable and Interrupt Priority SFRs
Symbolic
Address
IEP
Symbol
PFIFO
EDMA0
EDMA1
PDMA0
PDMA1
EFIFO
(MSB)
Position
IEP 7
IEP 6
IEP 5
IEP 4
IEP 3
IEP 2
IEP 1
IEP 0
PFIFO EDMA0 EDMA1 PDMA0 PDMA1 EFIFO
(LSB)
Function
(reserved)
(reserved)
FIFO Slave Bus Interface Interrupt Priority
DMA Channel 0 Interrupt Enable
DMA Channel 1 Interrupt Enable
DMA Channel 0 Priority
DMA Channel 1 Priority
FIFO Slave Bus Interface Interrupt Enable
Physical
Address
0F8H
Priority
Within a
Level
06
02
04
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