UPI-452 Datasheet, PDF (29/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
4 EXTERNAL DEMAND MODE
The DMA can be initiated by an external device via
External interrupt 0 and 1 (INT0 INT1) pins The
INT0 pin demands DMA0 (Channel 0) and INT1 de-
mands DMA1 (Channel 1) If the interrupts are con-
figured in edge mode a single byte transfer is ac-
complished for every request Interrupts also result
(INT0 and INT1) after every byte transfer (if en-
abled) If the interrupts are configured in level mode
the DMA transfer continues until the request goes
inactive or BCR ^e 0 In either case a DMA interrupt
is generated (if enabled) when BCR ^e 0 The GO bit
must be set for the transfer to begin
EXTERNAL MEMORY DMA
When transferring data to or from external memory
via DMA the HOLD (HLD) and HOLD-ACKNOWL-
EDGE (HLDA) signals are used for handshaking
The HOLD and HOLD-ACKNOWLEDGE are active
low signals which arbitrate control of the local bus
The UPI-452 can be used in a system where multi-
masters are connected to a single parallel Address
Data bus The HLD HLDA signals are used to share
resources (memory peripherals etc ) among all the
processors on the local bus The UPI-452 can be
configured in any of three different External Memory
Modes controlled by bits 5 and 6 (REQ ARB) in
the PCON SFR (Table 5) Each mode is described
below
REQUESTER MODE In this mode the UPI-452 is
not the bus master but must request the bus from
another device The UPI-452 configures port pin
P1 5 as a HLD output and pin P1 6 as a HLDA input
The UPI-452 issues a HLD signal when it needs ex-
ternal access for a DMA channel It uses the local
bus after receiving the HLDA signal from the bus
master and will not release the bus until its DMA
operation is complete
ARBITER MODE In this mode the UPI-452 is the
bus master It configures port pin P1 5 as HLD input
and pin P1 6 as HLDA output When a device as-
serts the HLD signal to use the local bus the UPI-
452 asserts the HLDA signal after current instruction
execution is complete If the UPI-452 needs an ex-
ternal access via a DMA channel it waits until the
requester releases the bus HLD goes inactive
DISABLE MODE When external program memory is
accessed by an instruction or by program counter
overflow beyond the internal ROM address or exter-
nal data memory is accessed by MOVX instructions
it is a local memory access and the HLD HLDA logic
is not initiated When a DMA channel attempts data
transfer to from the external data memory the
HLD HLDA logic is initiated as described below
DMA transfers from the internal memory space to
the internal memory space does not initiate the
HLD HLDA logic
The balance of the PCON SFR bits are described in
the ‘‘80C51 Register Description Power Control
SFR’’ section below
Latency
When the GO bit is set the UPI-452 finishes the
current instruction before starting the DMA opera-
tion Thus the maximum latency is 3 5 microseconds
(at 14 MHz)
DMA Interrupt Vectors
Each DMA channel has a unique vectored interrupt
associated with it There are two vectored interrupts
associated with the two DMA channels The DMA
interrupts are enabled and priorities set via the Inter-
rupt Enable and Priority SFR (see ‘‘Interrupts’’ sec-
tion) The interrupt priority scheme is similar to the
scheme in 80C51
Symbolic
Address
PCON
Definition
ARB
0
0
1
1
Table 5 DMA MODE CONTROL - PCON SFR
ARB REQ
(MSB)
Defined as per MLS-51 Data Sheet
Reset Status 00H
(LSB)
Physical
Address
87H
REQ
0
1
0
1
HLD HLDA logic is disabled
The UPI-452 is in the Requester Mode
The UPI-452 is in the Arbiter Mode
Invalid
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