UPI-452 Datasheet, PDF (30/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
When a DMA operation is complete (BCR decre-
ments to zero) the DONE flag in the respective
DCON (DCON0 or DCON1) SFR is set If the DMA
interrupt is enabled the DONE flag is reset automat-
ically upon vectoring to the interrupt routine
Interrupts When DMA is Active
If a Burst Mode DMA transfer is in progress the in-
terrupts are not serviced until the DMA transfer is
complete This is also true for level activated Exter-
nal Demand DMA transfers During Alternate Cycle
DMA transfers however the interrupts are serviced
at the end of the DMA cycle After that DMA cycles
and instruction execution cycles occur alternately In
the case of edge activated External Demand Mode
DMA transfers the interrupt is serviced at the end of
DMA transfer of that single byte
DMA Arbitration
Only one of the two DMA channels is active at a
time except when both are configured in the Alter-
nate Cycle mode In this case the DMA cycles and
Instruction Execution cycles occur in the following
order
1 DMA Cycle 0
2 Instruction execution
3 DMA Cycle 1
4 Instruction execution
DMA0 has priority over DMA1 during simultaneous
activation of the two DMA channels If one DMA
channel is active the other DMA channel if activat-
ed waits until the first one is complete
If DMA0 is already in the Alternate Cycle mode and
DMA1 is activated in Alternate Cycle Mode it will
take two instruction cycles before DMA1 is activated
(due to the priority of DMA0) Once DMA1 becomes
active the execution will follow the normal se-
quence
If DMA0 is already in the Alternate Cycle mode and
DMA1 is activated in Burst Mode the DMA1 Burst
transfer will follow the DMA0 Alternate Cycle trans-
fer (after the completion of the next instruction)
If the UPI-452 (as a Requester) asserts a HLD signal
to request a DMA transfer (see ‘‘External Memory
DMA’’)and its other DMA Channel requests a trans-
fer before the HLDA signal is received the channel
having higher priority is activated first A Burst Mode
transfer on channel 0 can not be interrupted since
DMA0 has the highest priority A Demand Mode
transfer on channel 0 is the only type of activity that
can interrupt a block transfer on DMA1
If while executing a DMA transfer the Arbiter re-
ceives a HLD signal and then before it can acknowl-
edge its other DMA Channel requests a transfer it
then completes the second DMA transfer before
sending the HLDA signal to release the bus to the
HLD request
DMA transfers may be held off under the following
conditions
1 A write to any of the DMA registers inhibits the
DMA for one instruction cycle
NOTE
An instruction cycle may be executed in 1 2 or 4
machine cycles dependent on the instruction being
executed DMA transfers are only executed after
the completion of an instruction cycle never be-
tween machine cycles of a single instruction cycle
Similarly instruction cycles are only executed upon
completion of a DMA transfer whether it be a one
machine cycle transfer or two machine cycles (for
ext to ext memory transfers)
2 A single machine cycle DMA register read opera-
tion (i e MOV A DCON0) will inhibit the DMA for
one instruction cycle However a two cycle DMA
register read operation will not inhibit the DMA
(i e MOV P1 DCON0)
If the HOLD HOLD Acknowledge logic is enabled in
requestor mode the hold request will go active once
the go bit has been set (for burst mode) and once
the demand flag is set (for demand mode) regard-
less of whether the DMA is held off by one of the
above conditions
The DMA Transfer waveforms are in Figures 8-11
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