UPI-452 Datasheet, PDF (18/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
HOST SLAVE INTERFACE SPECIAL FUNCTION REGISTERS
Slave Interface Special Function Registers
The Internal CPU interfaces with the FIFO slave module via the following registers
1) Mode Special Function Register (MODE)
2) Slave Control Special Function Register (SLCON)
3) Slave Status Special Function Register (SSTAT)
Each register resides in the SFR Array and is accessible via all direct addressing modes except bit Only the
Slave Control Register (SLCON) is bit addressable
1) MODE Special Function Register (MODE)
The MODE SFR provides the primary control of the external host-FIFO interface It is included in the SFR
Array so that the internal CPU can configure the external host-FIFO interface should the user decide that the
UPI-452 slave initialize itself independent of the external host CPU
The MODE SFR can be directly modified by the internal CPU through direct address instructions It can also be
indirectly modified by the external host CPU by setting up a MODE SFR service routine in the UPI-452 program
memory and having the host issue a Command either Immediate or DSC to vector to that routine
Symbolic
Physical
Address
Address
MODE
MD6
MD5
MD4
0F9H
(MSB)
Status On Reset
(LSB)
1
0
0
0
1
1
1
1
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
(reserved)
Request for Service to external CPU via
1 ^e DMA (DRQIN DRQOUT) request to external host when the Input or Output FIFO channel re-
quests service
0 ^e Interrupt (INTRQIN INTRQOUT or INTRQ) to external host when the Input or Output FIFO
channel requests service or a DSC is encountered in the I O Buffer Latch
Configure DRQIN INTRQIN and DRQOUT INTRQOUT to be either
1 ^e Enable (Actively driven)
0 ^e Disable (Tri-state)
Configure INTRQ to be either
1 ^e Enable (Actively driven)
0 ^e Disable (Tri-state)
(reserved)
(reserved)
(reserved)
(reserved)
2) Slave Control SFR (SLCON)
The Slave Control SFR is used to configure the FIFO-internal CPU interface All interrupts are to the internal
CPU
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