UPI-452 Datasheet, PDF (47/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
A C CHARACTERISTICS T_A ^e 0 C to 70 C V_CC ^e 5V g10% V_SS ^e 0V Load Capacitance for
Port 0 ALE and PSEN ^e 100 pF Load Capacitance for All Other Outputs ^e 80 pF
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
Parameter
14 MHz Osc
Min Max
Variable Oscillator
Min
Max
1 TCLCL Oscillator Frequency
35
14
TLHLL
ALE Pulse Width
103
2TCLCL^b40
TAVLL
Address Valid to ALE Low
(Note 1)
25
TCLCL^b55
TLLAX Address Hold after ALE Low
36
TCLCL^b35
TLLIV
ALE Low to Valid Instr In
185
4TCLCL^b100
TLLPL
ALE Low to PSEN Low
31
TCLCL^b40
TPLPH PSEN Pulse Width
169
3TCLCL^b45
TPLIV
PSEN Low to Valid Instr In
110
3TCLCL^b105
TPXIX
Input Instr Hold after PSEN
0
0
TPXIZ
Input Instr Float after PSEN
(Note 1)
57
TCLCL^b25
TAVIV
Address to Valid Instr In
252
5TCLCL^b105
TPLAZ PSEN Low to Address Float
10
10
TRLRH RD Pulse Width
329
6TCLCL^b100
TWLWH WR Pulse Width
329
6TCLCL^b100
TRLDV RD Low to Valid Data In
192
5TCLCL^b165
TRHDX Data Hold after RD
0
0
TRHDZ Data Float after RD
73
2TCLCL^b70
TLLDV ALE Low to Valid Data In
422
8TCLCL^b150
TAVDV Address to Valid Data In
478
9TCLCL^b165
TLLWL ALE Low to RD or WR Low
164 264 3TCLCL^b50 3TCLCL^a50
TAVWL Address Valid to RD or WR Low 156
4TCLCL^b130
TQVWX Data Valid to WR Transition
11
TCLCL^b60
TWHQX Data Hold after WR
21
TCLCL^b50
TRLAZ RD Low to Address Float
0
0
TWHLH RD or WR High to ALE High
31
111 TCLCL^b40 TCLCL^a40
TQVWH Data Valid to WR (Setup Time)
350
7TCLCL^b150
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
1 Use the value of 14 MHz specification or variable oscillator specification whichever is greater
47