UPI-452 Datasheet, PDF (20/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
SST7
SST6
SST5
SST4
SST3
SST2
SST1
SST0
Output FIFO Overrun Error Condition
1 ^e No Error
0 ^e Error (latched until Slave Status SFR is read)
Immediate Command Out Register Status
1 ^e Full (i e Host CPU has not read previous Immediate Command Out sent by internal CPU)
0 ^e Available
FIFO DMA Freeze Mode Status
1 ^e Normal Operation
0 ^e FIFO DMA Freeze Mode in Progress
Output FIFO Request for Service Flag
1 ^e Output FIFO does not request service
0 ^e Output FIFO requests service
Input FIFO Underrun Error Condition Flag
1 ^e No Underrun Error
0 ^e Underrun Error (latched until Slave Status SFR is read)
Immediate Command In SFR Status
1 ^e Empty
0 ^e Immediate Command received from host CPU
Data Stream Command Data at Input FIFO Flag
1 ^e Data (not DSC)
0 ^e DSC (at COMMAND IN SFR)
Input FIFO Request For Service Flag
1 ^e Input FIFO Does Not Request Service
0 ^e Input FIFO Request for Service
EXTERNAL HOST INTERFACE SPECIAL FUNCTION REGISTERS
The external host CPU has direct access to the following SFRs
1) Host Control Special Function Register
2) Host Status Special Function Register
It can also access other SFRs by commanding the internal CPU to change them accordingly via Data Stream
Commands or Immediate Commands The protocol for implementing this is entirely determined by the user
1) Host Control SFR (HCON)
By writing to the Host Control SFR the host can enable or disable FIFO interrupts and DMA requests and can
reset the UPI-452
Symbolic
Address
HCON
HC7
HC6 HC5 HC4 HC3
(MSB)
Status On Reset
0
0
0
0
0
0
Physical
Address
HC1
0E7H
(LSB)
0
0
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