UPI-452 Datasheet, PDF (13/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Input FIFO Channel
The Input FIFO Channel provides for data transfer from the external Host to the internal CPU (Figure 5) The
registers associated with the Input Channel during normal operation are listed in Table 1
Table 1 Input FIFO Channel Registers
Register Name
Description
1)
Input Buffer Latch
Host CPU Write only
2)
FIFO IN SFR
Internal CPU Read only
3)
COMMAND IN SFR
Internal CPU Read only
4)
Input FIFO Read Pointer SFR
Internal CPU Read only
5)
Input FIFO Write Pointer SFR
Internal CPU Read only
6)
Input FIFO Threshold SFR
Internal CPU Read only
See ‘‘FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE’’ section for FIFO DMA Freeze Mode SFR characteristics description
Figure 5 Input FIFO Channel Functional Block Diagram
231428 – 9
13