UPI-452 Datasheet, PDF (28/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
NOTE
All interrupts including FIFO interrupts are not rec-
ognized in Burst Mode Burst Mode transfers
should be used to service the FIFO only when the
user is certain that no Data Stream Commands are
in the block to be transferred (Input FIFO) and that
the FIFO contains enough space to store the block
to be transferred In all other cases Alternate Cycle
or Demand Mode should be used
3 FIFO AND SERIAL CHANNEL DEMAND
MODES
NOTES
1 If the output FIFO is configured as a one byte
buffer and the user program consists of two-cycle
instructions only then Alternate-Cycle Mode should
be used
2 In non-auto increment mode for internal to exter-
nal or external to internal transfers the lower 8 bits
of the external address should not correspond to
the FIFO or Serial Port address
FIFO Demand Mode
Although any DMA mode is possible using the FIFO
buffer only FIFO Demand and Alternate Cycle FIFO
Demand Modes are recommended FIFO Demand
Mode DMA transfers using the input FIFO Channel
are set-up by setting the GO bit and specifying the
FIFO IN register as the DMA Source Address Regis-
ter The BCR should be set to the maximum number
of expected transfers The user must also program
bit 1 of the Slave Control Register (SC1) to deter-
mine whether the Slave Status (SSTAT) SFR FIFO
Request For Service Flag will be activated when the
FIFO becomes not empty or full Once the Request
For Service Flag is activated by the FIFO the DMA
transfer begins and continues until the request flag
is deactivated While the request is active nothing
can interrupt the DMA (i e it behaves like burst
mode) The DMA Request is held active until one of
the following occurs
1) The FIFO becomes empty
2) A Data Stream Command is encountered (this
generates a FIFO interrupt and DMA operation
resumes after the Data Stream Command is
read)
3) BCR ^e 0 (this generates a DMA interrupt and
sets the DONE bit)
DMA transfers to the Output FIFO Channel are simi-
lar The FIFO OUT or COMMAND OUT SFR is the
DMA Destination Address SFR and a transfer is
started by setting the GO bit The user programs bit
0 of the Slave Control SFR (SC0) to determine
whether a demand occurs when the Output FIFO
is not full or empty DMA transfers begin when the
Request For Service Flag is activated by the FIFO
logic and continue as long as the flag is active The
Flag remains active until one of the following occurs
1) The FIFO becomes full
2) BCR ^e 0 (this generates a DMA interrupt and
sets the DONE bit)
As in Alternate Cycle FIFO Demand Mode the FIFO
logic resets the interrupt flag after transferring the
byte so the interrupt is never generated
After the GO bit is set the DMA is activated if one of
the following conditions takes place
SAR(0 1) ^e FIFO IN and HIFRS flag is set
DAR(0 1) ^e FIFO OUT and HOFRS flag is set
The HIFRS and HOFRS signals are internal flags
which are not accessible by software These flags
are similar to the SST0 and SST4 flags in the Slave
Status Register except that they are of the opposite
polarity and once set they are not cleared until the
Input FIFO becomes empty (HIFRS) or the Output
FIFO becomes full (HOFRS)
Serial Channel Demand Mode
Serial Channel Demand Mode is the logical choice
when using the Serial Port The DMAs can be acti-
vated by one of the Serial Channel Flags Receiver
interrupt (RI) or Transmitter Interrupt (TI)
SAR(0 1) ^e SBUF and RI flag is set
DAR(0 1) ^e SBUF and TI flag is set
NOTE
TI flag must be set by software to initiate the first
transfer
When the DMA transfer begins only one byte is
transferred at a time The serial port hardware auto-
matically resets the flag after completion of the
transfer so an interrupt will not be generated unless
DMA servicing is held off due to the DMA being
done (BCR ^e 0) or when the Hold Hold Acknowl-
edge logic is used and the DMA does not own the
bus In this case a Serial Port interrupt may be gen-
erated if enabled because of the status of the RI or
TI flags
In FIFO demand mode Alternate cycle FIFO de-
mand mode or Serial Port demand mode only one of
the following registers (SBUF FIN or FOUT) should
be used as either the SAR or DAR registers to pre-
vent undesired transfers For example if SAR0 ^e
FIN and DAR0 ^e SBUF in demand mode the DMA
transfer will start if either the HIFRS or TI flags are
set
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