UPI-452 Datasheet, PDF (8/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
UPI-452 PIN DESCRIPTIONS (Continued)
Symbol
Pin
Type
Name and Function
Port 1
(A0 – A7)
(HLD HLDA)
P1 0
7
1
6
2
5
3
4
4
3
5
2
6
1
P1 7
68
I O Port 1 is an 8-bit quasi-bi-directional I O port Port 1 can sink four
LS TTL inputs The alternate functions can only be activated if the
corresponding bit latch in the port SFR contains a 1 Otherwise the
port pin is stuck at 0 Pins P1 5 and P1 6 are multiplexed with HLD
and HLDA respectively whose functions are defined as below
Port Pin
Alternate Function
P1 5
HLD Local bus hold
input output signal
P1 6
HLDA Local bus hold
acknowledge input
Port 2
(A8 – A15)
P2 0
1
2
3
4
5
6
7
I O Port 2 is an 8-bit quasi-bi-directional I O port It also emits the high-
order 8 bits of address when accessing local expansion bus
29
external memory Port 2 can sink four LS TTL inputs
28
27
25
24
23
22
21
Port 3
P3 0
1
2
3
4
5
6
P3 7
I O Port 3 is an 8-bit quasi-bi-directional I O port It is also multiplexed
67
with the interrupt timer local serial channel RD and WR
66
functions that are used by various options The alternate functions
65
can only be activated if the corresponding bit latch in the port SFR
64
contains a 1 Otherwise the port pin is stuck at 0 Port 3 can sink
63
four LS TTL inputs The alternate functions assigned to the pins of
62
Port 3 are as follows
61
59
Port Pin
P3 0
Alternate Function
RxD
Serial input port
P3 1
TxD
Serial output port
P3 2
INT0
Interrupt 0 Input
P3 3
INT1
Interrupt 1 Input
P3 4
T0
Input to counter 0
P3 5
T1
Input to counter 1
P3 6
WR
The write control signal latches the
data from Port 0 outputs into the
External Data Memory on the
local bus
P3 7
RD
The read control signal latches the
data from Port 0 outputs on the
local bus
8