UPI-452 Datasheet, PDF (5/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
LIST OF TABLES AND FIGURES
Figures
1 Architectural Block Diagram
2
2 UPI 452 68-Pin PLCC Pinout Diagram
6
3 UPI-452 Conceptual Block Diagram
10
4 UPI-452 Functional Block Diagram
11
5 Input FIFO Channel Functional Block Diagram
13
6 Output FIFO Channel Functional Block Diagram
15
7a Handshake Mechanisms for Handling Immediate Command IN Flowchart
17
7b Handshake Mechanisms for Handling Immediate Command OUT Flowchart
17
8 DMA Transfer from External to External Memory
31
9 DMA Transfer from External to Internal Memory
31
10 DMA Transfer from Internal to External Memory
31
11 DMA Transfer Waveform Internal to Internal Memory
32
12 Disabling FIFO to Host Slave Interface Timing Diagram
36
Tables
1 Input FIFO Channel Registers
13
2 Output FIFO Channel Registers
15
3 UPI-452 Address Decoding
23
4 DMA Accessible Special Function Registers
26
5 DMA Mode Control - PCON SFR
29
6 Interrupt Priority
32
7 Interrupt Vector Addresses
32
8 Slave Bus Interface Status During FIFO DMA Freeze Mode
35
9 FIFO SFR’s Characteristics During FIFO DMA Freeze Mode
38
10 Threshold SFRs Range of Values and Number of Bytes to be Transferred
39
11a Internal Memory Addressing
41
11b 80C51 Special Function Registers
42
11c UPI-452 Additional Special Function Registers
42
12 Program Status Word (PSW)
44
13 PCON Special Function Register
44
5