UPI-452 Datasheet, PDF (33/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
A Data Stream Command Interrupt is generated
whenever there is a Data Stream Command in the
COMMAND IN SFR The interrupt is generated to
ensure that the internal interrupt is recognized be-
fore another instruction is executed
Immediate Command Interrupts
a An Immediate Command IN interrupt is generat-
ed if enabled to the internal CPU when the Host
has written to the Immediate Command IN (IMIN)
SFR The write operation clears the Slave Status
SFR bit (SSTAT SST2) and sets the Host Status
SFR bit (HSTAT HST2) to indicate that a byte is
present in the Immediate Command IN SFR
When the internal CPU reads the Immediate Com-
mand IN (IMIN) SFR the Slave Status SFR status
bit is set and the Host Status SFR status bit is
cleared indicating the IMIN SFR is empty Clear-
ing the Host Status SFR bit will cause a Request
For Service (INTRQ) interrupt if enabled to signal
the Host that the IMIN SFR is empty (See Figure
7a Immediate Command IN Flowchart )
b An Immediate Command OUT interrupt is gener-
ated if enabled to the internal CPU when the
Host has read the Immediate Command OUT
SFR The Host read causes the Slave Status
Immediate Command OUT bit (SSTAT SST6) to
be set and the corresponding Host Status bit
(HSTAT HST6) to be cleared indicating the SFR is
empty When the internal CPU writes to the Imme-
diate Command OUT SFR the Host Status bit is
set and Slave Status bit is cleared to indicate the
SFR is full (See Figure 7b Immediate Command
OUT Flowchart )
NOTE
Immediate Command IN and OUT interrupts are ac-
tually specific FIFO-Slave Interface interrupts to the
internal CPU
One instruction from the main program is executed
between two consecutive interrupt service routines
as in the 80C51 However if the second interrupt
service routine is due to a Data Stream Command
Interrupt the main program instruction is not execut-
ed (to prevent misreading of invalid data)
Interrupt Enabling and Priority
Each of the three interrupt special function registers
(IE IP and IEP) is listed below with its corresponding
bit definitions
Interrupt Enable SFR (IE)
Symbolic
Address
IE
EA
(MSB)
Symbol
EA
Position
IE 7
IE 6
IE 5
ES
IE 4
ET1
IE 3
EX1
IE 2
ET0
IE 1
EX0
IE 0
ES ET1 EX1 ET0 EX0
(LSB)
Physical
Address
0A8H
Function
Enables all interrupts If EA ^e 0 no interrupt will be
acknowledged If EA ^e 1 each interrupt source is
individually enabled or disabled by setting or clearing its
enable bit
(reserved)
(reserved)
Serial Channel interrupt enable
Internal Timer Counter 1 Overflow Interrupt
External Interrupt Request 1
Internal Timer Counter 0 Overflow Interrupt
External Interrupt Request 0
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