UPI-452 Datasheet, PDF (39/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Input and Output FIFO Threshold SFR
(ITHR OTHR)
The Input and Output FIFO Threshold SFRs are also
programmable by the internal CPU during FIFO DMA
Freeze Mode For proper operation of the Threshold
feature the Threshold SFR should be changed only
when the Input and Output FIFO channels are emp-
ty since they reflect the current number of bytes
available to read write before an interrupt is gener-
ated
Table 10 illustrates the Threshold SFRs range of
values and the number of bytes to be transferred
when the Request For Service Flag is activated
Table 10 Threshold SFRs Range of Values and
Number of Bytes to be Transferred
ITHR No of Bytes OTHR No of Bytes
(lower Available to (lower Available to
seven bits) be Written seven bits) be Read
0
1
2



CBP-3
CBP
CBP-1
CBP-2



3
2
3
3
4






(80H-CBP)-3 (80H-CBP)-2
(80H-CBP)-2 (80H-CBP)-1
(80H-CBP)-1 (80H-CBP)
The eighth bit of the Input and Output FIFO Thresh-
old SFR indicates the status of the service requests
regardless of the freeze condition If the eighth bit is
a ‘‘1’’ the FIFO is requesting service from the exter-
nal Host In other words when the Threshold SFR
value goes below zero (2’s complement) a service
request is generated The 8th bit of the ITHR SFR
must be set during initialization if the Host interrupt
request is desired immediately upon leaving Freeze
Mode Normally the ITHR SFR is decremented after
each external Host write to the Input FIFO and incre-
mented after each internal CPU read of the Input
FIFO The OTHR SFR is decremented by internal
CPU writes and incremented by external Host reads
Thus if the pointers are moved when the FIFO’s are
not empty these relationships can be used to calcu-
late the offset for the Threshold SFRs It is best to
change the Threshold SFRs only when the FIFO’s
are empty to avoid this complication The threshold
registers should also be updated after the pointers
have been manipulated
NOTE
The ITHR should only be programmed in the range
from 0 to (CBP-3) An ITHR value of (CBP-2) could
result in a failure to set the Input FIFO service re-
quest signal after the Input FIFO has been emptied
Correspondingly the OTHR should be programmed
in the range from 2 to (80H-CBP)-1 An OTHR
value of 1 could result in a failure to set the Output
FIFO service request after subsequent writes by the
UPI-452 have filled the Output FIFO
NOTE
When programming the ITHR SFR the eighth bit
should be set to 1 (OR’d with 80H) This causes
HSTAT SFR HST0 ^e 0 Input FIFO Request For
Service If ITHR bit 7 ^e 0 then HSTAT HST0 ^e 1
Input FIFO Does Not Request Service and no in-
terrupt will be generated
Host Status SFR (HSTAT)
When in FIFO DMA Freeze Mode some bits in the
Host Status SFR are forced high and will not reflect
the new status until the system returns to normal
operation The definition of the register in FIFO DMA
Freeze Mode is as follows
NOTE
The internal CPU reads this shadow latch value
when reading the Host Status SFR The shadow
latch will keep the information for these bits so nor-
mal operation can be resumed with the right status
The following bits are set (^e 1) when FIFO DMA
Freeze Mode is invoked
HST7 Output FIFO Error Condition Flag
1 ^e No error
0 ^e An invalid read has been done on the
output FIFO or the Immediate Command
Out Register by the host CPU
NOTE
The normal underrun error condition status is dis-
abled If an Immediate Command Out (IMOUT)
SFR read is attempted during FIFO DMA Freeze
Mode the contents of the IMOUT SFR is output on
the Data Buffer and the error status is cleared
(^e 0)
HST6 Immediate Command Out SFR Status
During normal operation this bit is cleared
(^e0) when the IMOUT SFR is written by the
UPI-452 internal CPU and set (^e 1) when the
IMOUT SFR is read by the external Host
Once the host-slave interface is frozen (i e
SST5 ^e 0) this bit will be read as a 1 by the
host CPU A shadow latch will keep the infor-
mation for this bit so normal operation can be
resumed with the correct status
Shadow latch
1 ^e Internal CPU reads the IMOUT SFR
0 ^e Internal CPU writes to the IMOUT SFR
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