UPI-452 Datasheet, PDF (37/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
External Host writing to the Immediate Command In
SFR and the Host Control SFR is also inhibited
when the slave bus interface is frozen Writing to
these two registers after FIFO DMA Freeze Mode is
invoked will also cause HST3 (overrun) to be activat-
ed (HST3^e0) Similarly reading the Immediate
Command Out Register by the external Host is dis-
abled during FIFO DMA Freeze Mode and any at-
tempt to do so will cause the clearing (deactivating
‘‘0’’) of HST7 bit (underrun)
After the slave bus interface is frozen the internal
CPU can perform the following operations on the
FIFO Special Function Registers (these operations
are allowed only during FIFO DMA Freeze Mode)
For FIFO
Reconfiguration
1 Changing the Channel
Boundary Pointer SFR
2 Changing the Input and
Output Threshold SFR
To Enhance the
Testability
3 Writing to the read and write
pointers of the Input and
Output FIFO’s
4 Writing to and reading the
Host Control SFRs
5 Controlling some bits of Host
and Slave Status SFRS
6 Reading the Immediate
Command Out SFR and
Writing to the Immediate
Comand In SFR
Description of each of these special
functions are as follows
FIFO Module SFRs During
FIFO DMA Freeze Mode
Table 9 summarizes the characteristics of all the
FIFO Special Function Registers during normal and
FIFO DMA Freeze Modes The registers that require
special treatment in FIFO DMA Freeze Mode are
HCON IWPR IRPR OWPR ORPR HSTAT
SSTAT MIN MOUT SFRs They can be described
in detail as follows
Host Control SFR (HCON)
During normal operation this register is written to or
read by the external Host However in FIFO DMA
Freeze Mode (i e SST5^e0) the UPI-452 internal
CPU has write access to the Host Control SFR and
write operations to this SFR by the external Host will
not be accepted If the Host attempts to write to
HCON the Input Channel error condition flag
(HST3) will be cleared
Input FIFO Pointer Registers
(IRPR IWPR)
Once the FIFO module is in FIFO DMA Freeze
Mode error flags due to overrun and underrun of the
Input FIFO pointers will be disabled Any attempt to
create an overrun or underrun condition by changing
the Input FIFO pointers would result in an inconsist-
ency in performance between the status flag and the
threshold counter
To enhance the speed of the UPI-452 read opera-
tions on the Input FIFO will look ahead by two bytes
Hence every time the IRPR is changed during FIFO
DMA Freeze Mode two NOPs need to be executed
so that the two byte pipeline can be updated with the
new data bytes pointed to by the new IRPR The
Threshold Counter SFR also needs to change by the
same number of bytes as the IRPR (increase
Threshold Counter if IRPR goes forward or decrease
if IRPR goes backward) This will ensure that future
interrupts will still be generated only after a thresh-
old number of bytes are available (See ‘‘Input and
Output FIFO Threshold SFR’’ section below )
In FIFO DMA Freeze Mode the internal CPU can
also change the content of IWPR and each change
of IWPR also requires an update of the Threshold
Counter SFR
Normally the internal CPU cannot write into the In-
put FIFO It can however during FIFO DMA Freeze
Mode by first reconfiguring the FIFO as an Output
FIFO (Refer to ‘‘Input and Output FIFO Threshold
SFR’’ section below) Changing the IRPR to be
equal to IWPR generates an empty condition while
changing IWPR to be equal to IRPR generates a full
condition The order in which the pointers are written
determines whether a full or empty condition is gen-
erated
Output FIFO Pointer SFR
(ORPR and OWPR)
In FIFO DMA Freeze Mode the contents of OWPR
can be changed by the internal CPU but each
change of OWPR or ORPR requires the Threshold
Counter SFR to be updated as described in the next
section A NOP must be executed whenever a new
value is written into ORPR as just described for
changes to IRPR As before changing ORPR to be
equal to OWPR will generate an empty condition
Output FIFO overrun or underrun condition cannot
be generated though The FIFO pointers should not
be set to a value outside of its range
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