UPI-452 Datasheet, PDF (50/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
1 TCLCL
Oscillator Frequency
35
TCHCX
High Time
20
TCLCX
Low Time
20
TCLCH
Rise Time
TCHCL
Fall Time
NOTE
External clock timings are sampled not tested on all parts
Max
14
20
20
Units
MHz
ns
ns
ns
ns
SERIAL PORT TIMING SHIFT REGISTER MODE
Test Conditions T_A ^e 0 C to 70 C V_CC ^e 5V g10% V_SS ^e 0V Load Capacitance ^e 80 pF
Symbol
Parameter
14 MHz Osc
Min Max
Variable Oscillator
Min
Max
Units
TXLXL⁽¹⁾ Serial Port Clock Cycle Time
857
12TCLCL
ns
TQVXH Output Data Setup to Clock Rising Edge 581
10TCLCL^b133
ns
TXHQX Output Data Hold after Clock Rising Edge 26
2TCLCL^b117
ns
TXHDX Input Data Hold after Clock Rising Edge
0
0
ns
TXHDV Clock Rising Edge to Input Data Valid
581
10TCLCL^b133 ns
NOTE
1 The tolerance of this signal is a function of the input oscillator frequency (TXLXL e 12TCLCL)
EXTERNAL CLOCK DRIVE WAVEFORM
AC TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
231428 – 23
231428 – 24
AC inputs during testing are driven at V_CC b0 5V for a logic ‘‘1’’
and 0 45V for a logic ‘‘0’’ Timing measurements are made at V_IH
min for a logic ‘‘1’’ and V_IL max for a logic ‘‘0’’
231428 – 25
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loaded V_OH V_OL level occurs
I_OL I_OH t g20 mA
50